User Tools

This is an old revision of the document!


FX3 Host Vendor Command Reference

The following tables provide information on how to access the camera's functionality for FX3 Host Vendor Command Interface. The address space is split into smaller chunks, grouped by common functionality:

0x00-0x9F

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Reserved0x00-0x9F Think of this as “system address space”

0xA0-0xA7

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Bootloader check0xA0 R/W Check if a bootloader is running, the result is in the command's status code (success/failure interpreted as true/false)
Reserved0xA1
Run DPC calibration0xA2 DPC ThresholdW/O Start the dynamic DPC calibration with the given DPC Threshold in range [0..255]
Reconfig FGPA0xA3 W/O Writing anything into this register causes the FPGA to reconfigure itself from SPI Flash
FPGA I²C Bridge0xA4FPGA register offsetFPGA data (write)R/W0 or 17:0 - FPGA dataFPGA write returns 0 byte buffer, FPGA read returns 1 byte buffer. Read/write is requested via control endpoint's direction attribute being set to DIR_FROM_DEVICE/DIR_TO_DEVICE.
For details on individual commands refer to FPGA I²C bridge
Sensor I²C bridge (8-bit configuration registers)0xA5 Sensor register mask and data (if writing) - see Notes column for details R/W0 or 1 7:0 - sensor register's data mask - an 8-bit MSB that specifies which bits to affect during a write operation - only the bits that are set in mask will be affected by bits in data. Setting mask to 0 ultimately turns a write operation into a read one as no bits are getting modified
data - an 8-bit LSB that specifies the new data to write into sensor's register. The write only affects the bits that are set in mask
Read operation returns an 8-bit register's value
Read/write is requested via control endpoint's direction attribute being set to DIR_FROM_DEVICE/DIR_TO_DEVICE.
For details on each sensor's register's function refer to the sensor's specification
Reserved for future I²C bridge 0xA6
RAW Mode Select0xA7 R/W 1 7:1 - Reserved
0 - RAW Mode
Select RAW Mode ('1') or Processed Video ('0')
N.B. This has been moved here from 0xA5 in FX3 version 46

This website uses cookies. By using the website, you agree with storing cookies on your computer. Also, you acknowledge that you have read and understand our Privacy Policy. If you do not agree, please leave the website.

More information