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| code:fx3_hvci_and_fpga_i_c_commands [2020/04/12 11:13] – [0x00-0x07 - FPGA general access] Igor Yefmov | code:fx3_hvci_and_fpga_i_c_commands [2020/05/14 22:05] – external edit 127.0.0.1 |
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| ====== FX3 Host Vendor Command Reference ====== | ====== FX3 Host Vendor Command Reference ====== |
| | Please refer to [[code::fx3_vr_cmd|Vendor Request Commands' reference]] page for details. |
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| The following tables provide information on how to access the camera's functionality for ''FX3 Host Vendor Command Interface''. The address space is split into smaller chunks, grouped by common functionality: | The following tables provide information on how to access the camera's functionality for ''FX3 Host Vendor Command Interface''. The address space is split into smaller chunks, grouped by common functionality: |
| |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| | |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| |
| |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| | |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| |
| |:::|:::|:::|''6'' on-board fan| (FX3-53+) ''1'' turns the on-board fan on, ''0'' turns it off | | |:::|:::|:::|''6'' on-board fan| (FPGA-72+) ''1'' turns the on-board fan on, ''0'' turns it off | |
| |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| | |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| |
| |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | | |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | |
