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| code:fpga_map_gen5 [2024/04/02 23:52] – [mFT lense access] Igor Yefmov | code:fpga_map_gen5 [2024/04/17 22:16] (current) – [Color grading] Igor Yefmov |
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| ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^ | ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^ |
| |''0x5000'0000''|:!: FPGA Version| 4 |R/O| see [[code#firmware_version_info|Firmware Version Info]] | | | |''0x5000'0000''|:!: FPGA Version| 4 |R/O| see [[code#firmware_version_info|Firmware Version Info]] | | |
| |''0x5000'0004''|:!: FPGA status| 4 |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' DPC done\\ ''0'' SFP active| The bytes of the FPGA status register are allocated according to the little-ending memory layout of the following C-style declaration. \\ For details on ''%%SpiCodeStruct%%'' see [[code:code#FPGA config status - SPI codes|SPI codes]]:\\ <code c++> | |''0x5000'0004''|:!: FPGA status| 4 |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' DPC done\\ ''0'' SFP active| The bytes of the FPGA status register are allocated according to the little-ending memory layout of the following C-style declaration((For details on ''spi_config_status'' see [[code:code#FPGA config status - SPI codes|SPI codes]])):\\ <code c++> |
| struct FpgaStatus{ | struct FpgaStatus{ |
| struct State{ | struct State{ |
| } state; | } state; |
| uint8_t core_temperature; | uint8_t core_temperature; |
| SpiCodeStruct config_status; | uint16_t spi_config_status; |
| };</code> | | };</code> | |
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| ^ Auto White-Balance adjustments ^^^^^ | ^ Auto White-Balance adjustments ^^^^^ |
| ^Address ^Name ^Bytes ^Access ^Notes ^ | ^Address ^Name ^Bytes ^Access ^Notes ^ |
| |''0x5000'0100''|:!: AWB Red adjustment| 2 |R/W|''int16_t'' value to add to Red channel. Default is \(0\)| | |''0x5000'0100''|:!: AWB Red adjustment| 2 |R/W|''int16_t'' value to add to Red component. Default is \(0\)| |
| |''0x5000'0104''|:!: AWB Green adjustment| 2 |R/W|''int16_t'' value to add to Green channel. Default is \(0\)| | |''0x5000'0104''|:!: AWB Green adjustment| 2 |R/W|''int16_t'' value to add to Green component. Default is \(0\)| |
| |''0x5000'0108''|:!: AWB Blue adjustment| 2 |R/W|''int16_t'' value to add to Blue channel. Default is \(0\)| | |''0x5000'0108''|:!: AWB Blue adjustment| 2 |R/W|''int16_t'' value to add to Blue component. Default is \(0\)| |
| |''0x5000'010C''|:!: AWB Red total| 4 | R/O | | | |''0x5000'010C''|:!: AWB Red total| 4 | R/O | | |
| |''0x5000'0110''|:!: AWB Green total| 4 | R/O | | | |''0x5000'0110''|:!: AWB Green total| 4 | R/O | | |
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| ===== Standard image adjustments ===== | ===== ISP adjustments ===== |
| ^ Standard image adjustments ^^^^^^^ | ^ Standard image adjustments ^^^^^^^ |
| ^Address ^Name ^Bytes ^Access ^Range ^Range description ^Neutral value ^ | ^Address ^Name ^Bytes ^Access ^Range ^Range description ^Neutral value ^ |
| ^ CMX ^^^^^ | ^ CMX ^^^^^ |
| ^Address ^Name ^Bytes ^Access ^Notes ^ | ^Address ^Name ^Bytes ^Access ^Notes ^ |
| |''0x80''|:!: CCM_00| 2 |R/W|\(CCM_{00}\)| | |''0x5000'0500''|:!: CCM_00| 2 |R/W|\(CCM_{00}\)| |
| |''0x84''|:!: CCM_01| 2 |R/W|\(CCM_{01}\)| | |''0x5000'0504''|:!: CCM_01| 2 |R/W|\(CCM_{01}\)| |
| |''0x88''|:!: CCM_02| 2 |R/W|\(CCM_{02}\)| | |''0x5000'0508''|:!: CCM_02| 2 |R/W|\(CCM_{02}\)| |
| |''0x8C''|:!: CCM_10| 2 |R/W|\(CCM_{10}\)| | |''0x5000'050C''|:!: CCM_10| 2 |R/W|\(CCM_{10}\)| |
| |''0x90''|:!: CCM_11| 2 |R/W|\(CCM_{11}\)| | |''0x5000'0510''|:!: CCM_11| 2 |R/W|\(CCM_{11}\)| |
| |''0x94''|:!: CCM_12| 2 |R/W|\(CCM_{12}\)| | |''0x5000'0514''|:!: CCM_12| 2 |R/W|\(CCM_{12}\)| |
| |''0x98''|:!: CCM_20| 2 |R/W|\(CCM_{20}\)| | |''0x5000'0518''|:!: CCM_20| 2 |R/W|\(CCM_{20}\)| |
| |''0x9C''|:!: CCM_21| 2 |R/W|\(CCM_{21}\)| | |''0x5000'051C''|:!: CCM_21| 2 |R/W|\(CCM_{21}\)| |
| |''0xA0''|:!: CCM_22| 2 |R/W|\(CCM_{22}\)| | |''0x5000'0520''|:!: CCM_22| 2 |R/W|\(CCM_{22}\)| |
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| ===== Color grading ===== | ===== Color grading ===== |
| |:::|:::|:::|''6:1'' index LSB| index into a page in the table | | |:::|:::|:::|''6:1'' index LSB| index into a page in the table | |
| |:::|:::|:::|''0'' access mode| ''0'': "normal mode", in which all the subsequent accesses to the register ''0x002F'' are governed by the values in ''0x002E''\\ ''1'': "bulk access", where after a read or write access to register ''0x002F'' the "Index" value will auto-increment by one so that the next read/wrie will access the subsequent table slot| | |:::|:::|:::|''0'' access mode| ''0'': "normal mode", in which all the subsequent accesses to the register ''0x002F'' are governed by the values in ''0x002E''\\ ''1'': "bulk access", where after a read or write access to register ''0x002F'' the "Index" value will auto-increment by one so that the next read/wrie will access the subsequent table slot| |
| |:!: Value|''0x2F''|R/W|''15:0'' value| 16 bits of either signed or unsigned integer value\\ - for a "Hue vs. Hue" table the 14 bits signed value is in range ''[-8192..+8192]'' which maps linearly into a Hue angle range ''-180°..+180°''\\ - for a "Hue vs. Saturation" table (as well as for similar tables %%LvS%% and %%SvS%%) the 12 bit unsigned value in range ''[0..+1280]'' maps linearly into a Saturation range ''[0%..1000%]'' where ''100%'' is the neutral position and ''0%'' produces a greyscale image\\ - (until FPGA v.72) for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 12 bit unsigned value in range ''[0..+4095]'' maps linearly into a Lightness absolute range ''[0..255]'' where ''0'' is pitch black and ''255'' is the maximum possible pixel luminosity value\\ - (starting with FPGA v.73) for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 13 bit signed value in range ''[-4096..+4095]'' maps linearly into a Lightness *relative* (adjustment) range ''[-256..255]'' where ''0'' is no adjustment to pixel luminosity value| | |:!: Value|''0x2F''|R/W|''15:0'' value| 16 bits of either signed or unsigned integer value\\ - for a "Hue vs. Hue" table the 14 bits signed value is in range ''[-8192..+8192]'' which maps linearly into a Hue angle range ''-180°..+180°''\\ - for a "Hue vs. Saturation" table (as well as for similar tables %%LvS%% and %%SvS%%) the 12 bit unsigned value in range ''[0..+1280]'' maps linearly into a Saturation range ''[0%..1000%]'' where ''100%'' is the neutral position and ''0%'' produces a greyscale image\\ - for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 13 bit signed value in range ''[-4096..+4095]'' maps linearly into a Lightness *relative* (adjustment) range ''[-256..255]'' where ''0'' is no adjustment to pixel luminosity value| |
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| ===== Media setup ===== | ===== Media setup ===== |
| ^Name ^Address ^Access ^Bit mapping ^Notes ^ | ^Name ^Address ^Access ^Bit mapping ^Notes ^ |
| |:!: Video output format|''0x32''|R/W|:!: ''7:4'' - UVC\\ :!: ''3:0'' - FPS code for SDI, SFP+, SDI|Bit depth for all video formats is set in register ''0x49''\\ UVC video formats:\\ :!:''0'' - "RAW" greyscale pre-debayer pixels\\ :!:''1'' - 4:4:4 RGB\\ :!:''2'' - (res) packed YCbCr 4:4:4\\ :!:''3'' - packed YCbCr 4:2:2\\ :!:''4'' - (res) packed YCbCr 4:2:0\\ :!:''5'' - (res) planar YCbCr 4:4:4\\ :!:''6'' - (res) planar YCbCr 4:2:2\\ :!:''7'' - planar YCbCr 4:2:0\\ :!:''8-15'' - (res) MJPEG, MPEG-x/H.26x, etc\\ \\ SDI/HDMI and SFP+ video output formats/FPS are always in unison. See [[code:fx3_hvci_and_fpga_i_c_commands#sdi_fps|SDI FPS]] table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format| | |:!: Video output format|''0x32''|R/W|:!: ''7:4'' - UVC\\ :!: ''3:0'' - FPS code for SDI, SFP+, SDI|Bit depth for all video formats is set in register ''0x49''\\ UVC video formats:\\ :!:''0'' - "RAW" greyscale pre-debayer pixels\\ :!:''1'' - 4:4:4 RGB\\ :!:''2'' - (res) packed YCbCr 4:4:4\\ :!:''3'' - packed YCbCr 4:2:2\\ :!:''4'' - (res) packed YCbCr 4:2:0\\ :!:''5'' - (res) planar YCbCr 4:4:4\\ :!:''6'' - (res) planar YCbCr 4:2:2\\ :!:''7'' - planar YCbCr 4:2:0\\ :!:''8-15'' - (res) MJPEG, MPEG-x/H.26x, etc\\ \\ SDI/HDMI and SFP+ video output formats/FPS are always in unison. See [[code:fx3_hvci_and_fpga_i_c_commands#sdi_fps|SDI FPS]] table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format| |
| |:!: Video output pixel bit depth|''0x33''|R/W|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit depths \(d_p\) is calculated from a 2-bit value \(N\) as: \[d_p = (N+4)*2\] Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC **only** supports ''8''-bit color depth, at least for now| | |:!: Video output pixel bit depth|''0x33''|R/W|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit values:\\ ''0'' => 8\\ ''1'' => 10\\ ''2'' => 12\\ ''3'' => 14\\ Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC currently **only** supports ''8''-bit color depth| |
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