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--- code:fpga_map_gen5 [2024/04/02 23:12] – [Image stats] Igor Yefmov
+++ code:fpga_map_gen5 [2024/04/17 22:16] (current) – [Color grading] Igor Yefmov
@@ Line 16: / Line 16: @@
 The address space is broken down into smaller chunks, grouped by common functionality:
 ===== FPGA basic status and controls =====
+^  FPGA basic status and controls  ^^^^^^
 ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^
 |''0x5000'0000''|:!: FPGA Version|  4  |R/O| see [[code#firmware_version_info|Firmware Version Info]] | |
-|''0x5000'0004''|:!: FPGA status|  4  |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' DPC done\\ ''0'' SFP active| The bytes of the FPGA status register are allocated according to the little-ending memory layout of the following C-style declaration. \\ For details on ''%%SpiCodeStruct%%'' see [[code:code#FPGA config status - SPI codes|SPI codes]]:\\ <code c++>
+|''0x5000'0004''|:!: FPGA status|  4  |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' DPC done\\ ''0'' SFP active| The bytes of the FPGA status register are allocated according to the little-ending memory layout of the following C-style declaration((For details on ''spi_config_status'' see [[code:code#FPGA config status - SPI codes|SPI codes]])):\\ <code c++>
 struct FpgaStatus{
   struct State{
@@ Line 29: / Line 30: @@
   } state;
   uint8_t core_temperature;
-  SpiCodeStruct config_status;
+  uint16_t spi_config_status;
 };</code> |
 ===== FPGA operation mode =====
-The bits in these 4 bytes allow to change the operation mode of the FPGA (for example enabling new firmware to be written into SPI flash) and enable individual media output channels and/or specific transformation blocks:
+^  FPGA operation mode((Set the operation mode of the FPGA (e.g. switch into firmware programming) and enable/disable individual media output channels and specific transformation blocks))  ^^^^^^
 ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^
-|''0x5000'0008''|:!: FPGA operation mode|  4  |R/W|''31:18'' reserved| |
+|''0x5000'0008''|:!: FPGA operation mode|  4  |R/W|''31:20'' reserved| |
-|:::|:::|:::|:::|:!: ''17'' CCM| enable Color Correction Matrix transformation block |
+|:::|:::|:::|:::|:!: ''19'' CCM| enable Color Correction Matrix transformation block |
-|:::|:::|:::|:::|:!: ''16'' Gamma| enable UVC Gamma transformation block |
+|:::|:::|:::|:::|:!: ''18'' Gamma| enable UVC Gamma transformation block |
+|:::|:::|:::|:::|:!: ''17:16'' debayer strategy|**De-mosaicing strategy** directs the use of a specific implementation of color reconstruction:\\ ''0'' - use "branchless 5x5", like the one [[https://www.ipol.im/pub/art/2011/g_mhcd/article.pdf|described in here]]\\ ''1'' - use "branching 5x5", for example the one [[http://www.siliconimaging.com/RGB%20Bayer.htm|described here]]\\ ''2'', ''3'' - reserved|
 |:::|:::|:::|:::| ''15'' reserved| |
 |:::|:::|:::|:::|:!: ''14'' reserved (headphones)| |
@@ Line 54: / Line 56: @@
 ===== AWB =====
-Info for performing Auto White-Balance adjustments on the image
+^  Auto White-Balance adjustments  ^^^^^
 ^Address ^Name ^Bytes ^Access ^Notes ^
-|''0x5000'0100''|:!: AWB Red adjustment|  2  |R/W|a signed 16-bit value to add to every pixel in Red channel. Default is \(0\)|
+|''0x5000'0100''|:!: AWB Red adjustment|  2  |R/W|''int16_t'' value to add to Red component. Default is \(0\)|
-|''0x5000'0104''|:!: AWB Green adjustment|  2  |R/W|a signed 16-bit value to add to every pixel in Green channel. Default is \(0\)|
+|''0x5000'0104''|:!: AWB Green adjustment|  2  |R/W|''int16_t'' value to add to Green component. Default is \(0\)|
-|''0x5000'0108''|:!: AWB Blue adjustment|  2  |R/W|a signed 16-bit value to add to every pixel in Blue channel. Default is \(0\)|
+|''0x5000'0108''|:!: AWB Blue adjustment|  2  |R/W|''int16_t'' value to add to Blue component. Default is \(0\)|
 |''0x5000'010C''|:!: AWB Red total|  4  | R/O | |
 |''0x5000'0110''|:!: AWB Green total|  4  | R/O | |
@@ Line 67: / Line 68: @@
-===== Standard image adjustments =====
+===== ISP adjustments =====
+^  Standard image adjustments  ^^^^^^^
 ^Address ^Name ^Bytes ^Access ^Range ^Range description ^Neutral value ^
 |''0x5000'0200''|:!: Brightness|  2  |R/W|\([-1024..1023]\) |\(-1024\) makes the image very dark\\ \(1023\) makes the image very bright |\(0\) |
@@ Line 89: / Line 91: @@
 =====  Color Correction Matrix (a.k.a. CCM or CMX)  =====
-See [[isp:ccm|Color correction matrix]] article in this Wiki's ISP section for more details. The 16-bit (MSB-LSB) value is defined as 7+9 bits, where MSB[7:1] are the integer part and MSB[0]LSB[7:0] is the fractional part (effectively that value is 512 times larger than the original fractional part)
+See [[isp:ccm|Color correction matrix]] article in this Wiki's ISP section for more details. The 16-bit (MSB-LSB) value is defined as \(7+9\) bits, where MSB''[7:1]'' are the integer part and MSB''[0]''LSB''[7:0]'' is the fractional part (effectively that value is 512 times larger than the original fractional part)
+^  CMX  ^^^^^
 ^Address ^Name ^Bytes ^Access ^Notes ^
-|''0x80''|:!: CCM_00|  2  |R/W|\(CCM_{00}\)|
+|''0x5000'0500''|:!: CCM_00|  2  |R/W|\(CCM_{00}\)|
-|''0x84''|:!: CCM_01|  2  |R/W|\(CCM_{01}\)|
+|''0x5000'0504''|:!: CCM_01|  2  |R/W|\(CCM_{01}\)|
-|''0x88''|:!: CCM_02|  2  |R/W|\(CCM_{02}\)|
+|''0x5000'0508''|:!: CCM_02|  2  |R/W|\(CCM_{02}\)|
-|''0x8C''|:!: CCM_10|  2  |R/W|\(CCM_{10}\)|
+|''0x5000'050C''|:!: CCM_10|  2  |R/W|\(CCM_{10}\)|
-|''0x90''|:!: CCM_11|  2  |R/W|\(CCM_{11}\)|
+|''0x5000'0510''|:!: CCM_11|  2  |R/W|\(CCM_{11}\)|
-|''0x94''|:!: CCM_12|  2  |R/W|\(CCM_{12}\)|
+|''0x5000'0514''|:!: CCM_12|  2  |R/W|\(CCM_{12}\)|
-|''0x98''|:!: CCM_20|  2  |R/W|\(CCM_{20}\)|
+|''0x5000'0518''|:!: CCM_20|  2  |R/W|\(CCM_{20}\)|
-|''0x9C''|:!: CCM_21|  2  |R/W|\(CCM_{21}\)|
+|''0x5000'051C''|:!: CCM_21|  2  |R/W|\(CCM_{21}\)|
-|''0xA0''|:!: CCM_22|  2  |R/W|\(CCM_{22}\)|
+|''0x5000'0520''|:!: CCM_22|  2  |R/W|\(CCM_{22}\)|
 ===== Color grading =====
@@ Line 109: / Line 111: @@
 |:::|:::|:::|''6:1'' index LSB| index into a page in the table |
 |:::|:::|:::|''0'' access mode| ''0'': "normal mode", in which all the subsequent accesses to the register ''0x002F'' are governed by the values in ''0x002E''\\ ''1'': "bulk access", where after a read or write access to register ''0x002F'' the "Index" value will auto-increment by one so that the next read/wrie will access the subsequent table slot|
-|:!: Value|''0x2F''|R/W|''15:0'' value| 16 bits of either signed or unsigned integer value\\  - for a "Hue vs. Hue" table the 14 bits signed value is in range ''[-8192..+8192]'' which maps linearly into a Hue angle range ''-180°..+180°''\\  - for a "Hue vs. Saturation" table (as well as for similar tables %%LvS%% and %%SvS%%) the 12 bit unsigned value in range ''[0..+1280]'' maps linearly into a Saturation range ''[0%..1000%]'' where ''100%'' is the neutral position and ''0%'' produces a greyscale image\\  - (until FPGA v.72) for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 12 bit unsigned value in range ''[0..+4095]'' maps linearly into a Lightness absolute range ''[0..255]'' where ''0'' is pitch black and ''255'' is the maximum possible pixel luminosity value\\  - (starting with FPGA v.73) for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 13 bit signed value in range ''[-4096..+4095]'' maps linearly into a Lightness *relative* (adjustment) range ''[-256..255]'' where ''0'' is no adjustment to pixel luminosity value|
+|:!: Value|''0x2F''|R/W|''15:0'' value| 16 bits of either signed or unsigned integer value\\  - for a "Hue vs. Hue" table the 14 bits signed value is in range ''[-8192..+8192]'' which maps linearly into a Hue angle range ''-180°..+180°''\\  - for a "Hue vs. Saturation" table (as well as for similar tables %%LvS%% and %%SvS%%) the 12 bit unsigned value in range ''[0..+1280]'' maps linearly into a Saturation range ''[0%..1000%]'' where ''100%'' is the neutral position and ''0%'' produces a greyscale image\\  - for a "Lightness vs. Lightness" table (as well as for similar table %%HvL%%) the 13 bit signed value in range ''[-4096..+4095]'' maps linearly into a Lightness *relative* (adjustment) range ''[-256..255]'' where ''0'' is no adjustment to pixel luminosity value|
 ===== Media setup =====
@@ Line 116: / Line 118: @@
 ^Name ^Address ^Access ^Bit mapping ^Notes ^
 |:!: Video output format|''0x32''|R/W|:!: ''7:4'' - UVC\\ :!: ''3:0'' - FPS code for SDI, SFP+, SDI|Bit depth for all video formats is set in register ''0x49''\\ UVC video formats:\\ :!:''0'' - "RAW" greyscale pre-debayer pixels\\ :!:''1'' - 4:4:4 RGB\\ :!:''2'' - (res) packed YCbCr 4:4:4\\ :!:''3'' - packed YCbCr 4:2:2\\ :!:''4'' - (res) packed YCbCr 4:2:0\\ :!:''5'' - (res) planar YCbCr 4:4:4\\ :!:''6'' - (res) planar YCbCr 4:2:2\\ :!:''7'' - planar YCbCr 4:2:0\\ :!:''8-15'' - (res) MJPEG, MPEG-x/H.26x, etc\\ \\ SDI/HDMI and SFP+ video output formats/FPS are always in unison. See [[code:fx3_hvci_and_fpga_i_c_commands#sdi_fps|SDI FPS]] table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format|
-|:!: Video output pixel bit depth|''0x33''|R/W|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit depths \(d_p\) is calculated from a 2-bit value \(N\) as: \[d_p = (N+4)*2\] Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC **only** supports ''8''-bit color depth, at least for now|
+|:!: Video output pixel bit depth|''0x33''|R/W|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit values:\\ ''0'' => 8\\ ''1'' => 10\\ ''2'' => 12\\ ''3'' => 14\\ Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC currently **only** supports ''8''-bit color depth|
-==== Image sensor config ====
-^Name ^Address ^Access ^Bit mapping ^Notes ^
-|:!: Image sensor configuration|''0x34''|R/W|''7:2'' - res\\ :!: ''1:0'' - de-mosaicing strategy|**De-mosaicing strategy** directs the use of a specific implementation of color reconstruction:\\ ''3'', ''2'' - reserved\\ ''1'' - use "branching 5x5", for example the one [[http://www.siliconimaging.com/RGB%20Bayer.htm|described here]]\\ ''0'' - use "branchless 5x5", like the one [[https://www.ipol.im/pub/art/2011/g_mhcd/article.pdf|described in here]]|
-|Reserved|''0x35-0x39''| | | |
 ==== FOURCC formats (for UVC) ====
-A combination of data in ''0x0033[1:0]'' (pixel bit depth) and ''0x32[7:4]'' (video format) used for UVC is mapped into standard FOURCC codes as summarized in the following table:
+^  UVC's FOURCC codes((A combination of pixel bit depth and video format used for UVC is mapped into standard FOURCC codes as summarized in the following table))  ^^^^^^
-^''0x0033[1:0]''\''0x0032[7:4]'' ^''0'' (RAW) ^''1'' (RGB) ^''2'' (packed YUV 4:4:4((ordering is UYV))) ^''3'' (packed YUV 4:2:2((macropixel byte ordering: Y0U0Y1V0))) ^''7'' (planar YUV 4:2:0((chroma plane is a interleaved set of U/V samples))) ^
+^\(_{bit-depth} \backslash ^{video-format}\) ^''0'' (RAW) ^''1'' (RGB) ^''2'' (packed YUV 4:4:4((ordering is UYV))) ^''3'' (packed YUV 4:2:2((macropixel byte ordering: Y0U0Y1V0))) ^''7'' (planar YUV 4:2:0((chroma plane is a interleaved set of U/V samples))) ^
 ^''0'' (8 bit) |:!: BA81/BYR1/GREY/Y8/Y800 (8bpp)|:!: BI_RGB/RGB (24bpp) |:!: Y444/IYU2 (24bpp) |:!: YUY2/YUYV (16 bpp)|:!: NV12 (12bpp)|
 ^''1'' (10 bit) |:!: Y10((need to register with MS)) (16bpp((not 10)))|:!: BI_BITFIELDS (48bpp) |:!: Y410 (32bpp((includes 2 bit alpha at [31:30]))) |:!: Y210 (32bpp)\\ YUVP?/Y42T (24bpp?)|:!: P010 (32bpp) |
@@ Line 132: / Line 129: @@
 ^''3'' (14 bit) |:!: Y16((yes, 16, not 14)) (16bpp((not 14)))|:!: BI_BITFIELDS (48bpp) |:!: Y414((need to register with MS)) (48bpp((or 42?))) |:!: Y214((need to register with MS)) (32bpp((or 28?))) |:!: P014((need to register with MS)) (32bpp((or 21?))) |
-==== SDI FPS ====
+==== SDI FPS and pixel clock ====
-FPS+resolution pair dictates an SDI pixel clock choice according to this table:
+^  SDI FPS and pixel clock((FPS+resolution pair dictates an SDI pixel clock choice))  ^^^^
-^ code (FPS)  ^  1920x1080  ^  3840x2160  ^  7680x4320  ^
+^ \(_{code (FPS)} \backslash ^{resolution}\)  ^  1920x1080  ^  3840x2160  ^  7680x4320  ^
 | ''0x01'' (23.98)  |  74.18  |  296.70  | |
 | ''0x02'' (24)  |  74.25  |  297  |  1188  |
@@ Line 182: / Line 179: @@
 ==== mFT lense access ====
-FIXME Need to totally rewrite FIXME
+^  mFT lense access  ^^^^^
 ^Address  ^Name ^Bytes ^Access ^Notes ^
 |''0x4805'0000''|MFT command|  4  |R/W|<code c++>

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