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| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision | ||
| support:firware_revision_history [2020/03/17 15:30] – Igor Yefmov | support:firware_revision_history [2020/04/15 22:22] – Igor Yefmov | ||
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| Line 2: | Line 2: | ||
| ===== FX3 ===== | ===== FX3 ===== | ||
| + | ==== 53 ==== | ||
| + | * " | ||
| + | * UVC White Balance temperature limit increased to 7000°K | ||
| + | * improved stability (no more race condition in UVC handler code) | ||
| + | * on-board fan now turns on if a module is plugged into SFP+ cage and is active | ||
| + | * a lot of code refactoring | ||
| + | |||
| ==== 52 ==== | ==== 52 ==== | ||
| * **Previous settings' | * **Previous settings' | ||
| Line 31: | Line 38: | ||
| ===== FPGA ===== | ===== FPGA ===== | ||
| + | ==== 72 ==== | ||
| + | * on-board fan is now controlled via bit #6 of control register (0x06) | ||
| + | * the code is now built using Vivado 2019 (and uses some fewer transistors as a result) | ||
| + | |||
| ==== 71 ==== | ==== 71 ==== | ||
| * Support for the " | * Support for the " | ||