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support:firware_revision_history [2020/03/17 10:58] – created Igor Yefmov | support:firware_revision_history [2020/04/15 22:22] – Igor Yefmov | ||
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===== FX3 ===== | ===== FX3 ===== | ||
+ | ==== 53 ==== | ||
+ | * " | ||
+ | * UVC White Balance temperature limit increased to 7000°K | ||
+ | * improved stability (no more race condition in UVC handler code) | ||
+ | * on-board fan now turns on if a module is plugged into SFP+ cage and is active | ||
+ | * a lot of code refactoring | ||
+ | |||
==== 52 ==== | ==== 52 ==== | ||
+ | * **Previous settings' | ||
* Support for the " | * Support for the " | ||
* Color Grading writes into FPGA are now processed asynchronously (for example an LvL full load results in 1,345 I²C bus requests!) | * Color Grading writes into FPGA are now processed asynchronously (for example an LvL full load results in 1,345 I²C bus requests!) | ||
Line 30: | Line 38: | ||
===== FPGA ===== | ===== FPGA ===== | ||
+ | ==== 72 ==== | ||
+ | * on-board fan is now controlled via bit #6 of control register (0x06) | ||
+ | * the code is now built using Vivado 2019 (and uses some fewer transistors as a result) | ||
+ | |||
==== 71 ==== | ==== 71 ==== | ||
* Support for the " | * Support for the " |