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support:firware_revision_history [2020/04/15 22:22] Igor Yefmovsupport:firware_revision_history [2020/04/15 22:54] – [53] Igor Yefmov
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   * UVC White Balance temperature limit increased to 7000°K   * UVC White Balance temperature limit increased to 7000°K
   * improved stability (no more race condition in UVC handler code)   * improved stability (no more race condition in UVC handler code)
-  * on-board fan now turns on if a module is plugged into SFP+ cage and is active+  * on-board fan now turns on if a module is plugged into SFP+ cage and is active (requires FPGA v.72+)
   * a lot of code refactoring   * a lot of code refactoring
  

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