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The following tables provide information on how to access the camera's functionality for FX3 Host Vendor Command Interface and an FPGA I²C bridge:
FX3 Host Vendor Command Reference
| Name | Offset | wIndex | wValue | Access type | Byte length | Return buffer bits | Notes |
|---|---|---|---|---|---|---|---|
| Bootloader check | 0xA0 | R/W | Check if a bootloader is running, the result is in the command's status code (success/failure interpreted as true/false) |
||||
| Reserved | 0xA1 | ||||||
| Run DPC calibration | 0xA2 | DPC Threshold | W/O | Start the dynamic DPC calibration with the given DPC Threshold in range [0..255] | |||
| Reconfig FGPA | 0xA3 | W/O | Writing anything into this register causes the FPGA to reconfigure itself from SPI Flash | ||||
| FPGA I²C Bridge | 0xA4 | FPGA register offset | FPGA data (write) | W/O | 0 or 1 | 7:0 - FPGA data | FPGA write returns 0 byte buffer, FPGA read returns 1 byte buffer. Read/write is requested via control endpoint's direction attribute being set to DIR_FROM_DEVICE/DIR_TO_DEVICE. For more details refer to FPGA I²C bridge |
| Reserved | 0xA5-0xA9 | ||||||
| Erase SPI Flash | 0xAA | W/O | Any write to this location invalidates the FX3 SPI Flash and causes the FX3 to reset itself to a bootloader mode for reprogramming | ||||
| FX3 version | 0xAB | R/O | 4 | 31:29 Vendor id28:24 HW_CFG_ID23:16 Product id15:11 Release type10:0 Build number | Get detailed version information of the FX3, for more details refer to FX3VersionInfo | ||
| FPGA version | 0xAC | R/O | 4 | 31:29 Vendor id28:24 HW_CFG_ID23:16 Product id15:11 Release type10:0 Build number | Get detailed version information of the FPGA, for more details refer to FPGAVersionInfo | ||
| FPGA config. ctrl. | 0xAD | W/O | Any write to this location will put the FPGA into configuration mode | ||||
| FPGA config. status - SPI codes | 0xAE | R/O | 2 | 15 Program SwitchWord OK14 Verify OK13 Program OK12 Erase OK11 Erase SwitchWord OK10 Check ID OK9 Initialize OK8 Config started7 CRC error6 Timeout error5 Program error4 Erase error3 IdCode error2 Config error1 Config done0 Config not busy | Retrieve detailed status of the FPGA configuration operation | ||
| SPI Flash write enable | 0xAF | W/O | Reconfigure the FX3 IOMatrix to disable GPIF and enable SPI | ||||
| Reserved | 0xB0-0xDF | ||||||
| FX3 reset | 0xE0 | R/W | Cypress vendor command to soft reset FX3 | ||||
| Reserved | 0xE1-0xFF |
FPGA I²C bridge
| Name | Offset | Access | Bit mapping | Notes |
|---|---|---|---|---|
| FPGA Version #0 | 0x00 | R/O | 7:5 Vendor id4:0 HW_CFG_ID | |
| FPGA Version #1 | 0x01 | R/O | 7:0 Product id | |
| FPGA Version #2 | 0x02 | R/O | 7:3 Release type2:0 Build number MSB | Build number is split into 2 MSB and 8 LSB for a combined total width of 10 bits |
| FPGA Version #3 | 0x03 | R/O | 7:0 Build number LSB |
|
| FPGA config status #0 - SPI codes | 0x04 | R/O | 7 CRC error6 Timeout error5 Program error4 Erase error3 IdCode error2 Config error1 Config done0 Config not busy | |
| FPGA config status #1 - SPI codes | 0x05 | R/O | 7 Program SwitchWord OK6 Verify OK5 Program OK4 Erase OK3 Erase SwitchWord OK2 Check ID OK1 Initialize OK0 Config started | |
| FPGA control | 0x06 | R/W | 7 FPGA config enable6:4 Reserved3 DPC enable2 HSUB enable1 Audio enable0 Video enable | If bit 7 is set the GPIF becomes read only and waits for an update bitstreamSetting bit 3 along with bit 0x06::0 will perform a DPC correctionBit 2 is to enable/disable Horisontal SubsamplingBit 1 is to enable/disable on-board microphonesBit 0 enables/disables video streaming |
| Reserved | 0x07 | |||
| LED_RED_L | 0x08 | R/W | 7:0 Red LED | LSB of LED's red intensity in range [0..255] |
| LED_RED_H | 0x09 | R/W | Reserved | |
| LED_GREEN_L | 0x0A | R/W | 7:0 Green LED | LSB of LED's green intensity in range [0..255] |
| LED_GREEN_H | 0x0B | R/W | Reserved | |
| LED_BLUE_L | 0x0C | R/W | 7:0 Blue LED | LSB of LED's blue intensity in range [0..255] |
| LED_BLUE_H | 0x0D | R/W | Reserved | |
| Reserved | 0x0E-0x0F | |||
| Brightness_L | 0x10 | R/W | 7:0 LSB | 16 bits of brightness are split into 8 bits of LSB and MSB |
| Brightness_H | 0x11 | R/W | 7:0 MSB |
|
| Contrast_L | 0x12 | R/W | 7:0 LSB | 16 bits of contrast are split into 8 bits of LSB and MSB |
| Contrast_H | 0x13 | R/W | 7:0 MSB |
|
| Saturation_L | 0x14 | R/W | 7:0 LSB | 16 bits of Saturation are split into 8 bits of LSB and MSB |
| Saturation_H | 0x15 | R/W | 7:0 MSB |
|
| Sharpness_L | 0x16 | R/W | 7:0 LSB | 16 bits of Sharpness are split into 8 bits of LSB and MSB |
| Sharpness_H | 0x17 | R/W | 7:0 MSB |
|
| Gamma_L | 0x18 | R/W | 7:0 LSB | 16 bits of Gamma are split into 8 bits of LSB and MSB |
| Gamma_H | 0x19 | R/W | 7:0 MSB |
|
| Hue_L | 0x1A | R/W | 7:0 LSB | 16 bits of Hue are split into 8 bits of LSB and MSB |
| Hue_H | 0x1B | R/W | 7:0 MSB |
|
| Reserved | 0x1C-0x1F | |||
| DPC Threshold LSB | 0x20 | R/W | 7:0 LSB | 16 bit of DPC (defective pixel cancellation) Threshold are split into 8 bits of LSB and MSB |
| DPS Threshold MSB | 0x21 | R/W | 7:0 MSB |
|
| DPC count LSB | 0x22 | R/O | 7:0 LSB | Once the DPC calibration is done the 16-bit value is stored in these 2 registers |
| DPC count MSB | 0x23 | R/O | 7:0 MSB |
|
| Reserved | 0x24-0x27 | |||
| Y average | 0x28 | R/O | 7:0 value | |
0x29 | ||||
0x2A | ||||
| R average | 0x29 | R/O | 7:0 value | an average RGB value |
| G average | 0x2A | R/O | 7:0 value |
|
| B average | 0x2B | R/O | 7:0 value |
|
| Reserved | 0x2C-0x2F | |||
| CAM_GPIO_L | 0x30 | R/W | reserved | |
| CAM_GPIO_H | 0x31 | R/W | reserved | |
| CAM_GPIO_DIR_L | 0x32 | R/W | reserved | |
| CAM_GPIO_DIR_H | 0x33 | R/W | reserved | |
| CAM_GPIO_OE_L | 0x34 | R/W | reserved | |
| CAM_GPIO_OE_H | 0x35 | R/W | reserved | |
| Reserved | 0x36-0x3F | |||
| H.264 QP | 0x40 | R/W | 7:6 reserved5:0 value | Valid range for the H.264 QP value is [0..51] |
| Reserved | 0x41-0x7F | |||
| “Green screen”, a.k.a. “Chroma Key” on-board optimization is designed to replace a range of colors with a single well-defined one | ||||
| CK control | 0x80 | R/W | 7:1 reserved0 enable | enable/disable Chroma Key control |
| CK status | 0x81 | reserved | ||
| CK saturation LSB | 0x82 | R/W | 7:0 LSB | only the LSB 8 bits are used right now for the range [0..255] to specify the minimum saturation threshold |
| CK saturation MSB | 0x83 | R/W | reserved | |
| CK luma LSB | 0x84 | R/W | reserved | |
| CK luma MSB | 0x85 | R/W | reserved | |
| CK hue LSB | 0x86 | R/W | 7:0 hue LSB | 14 bits of a signed hue value are split into 8 LSB and 6 MSB |
| CK hue MSB | 0x87 | R/W | 7:6 reserved5:0 hue MSB |
|
| CK tolerance LSB | 0x88 | R/W | 7:0 tolerance LSB | 13 bits of an unsigned hue tolerance value are split into 8 LSB and 5 MSB |
| CK tolerance MSB | 0x89 | R/W | 7:5 reserved4:0 tolerance MSB |
|
| CK red LSB | 0x8A | R/W | 7:0 red LSB | |
| CK red MSB | 0x8B | R/W | reserved | |
| CK green LSB | 0x8C | R/W | 7:0 green LSB | |
| CK green MSB | 0x8D | R/W | reserved | |
| CK blue LSB | 0x8E | R/W | 7:0 blue LSB | |
| CK blue MSB | 0x8F | R/W | reserved | |