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| code:fx3_hvci_and_fpga_i_c_commands [2019/11/13 00:27] – [0xA8-0xA9 - sysinfo and debugging] Igor Yefmov | code:fx3_hvci_and_fpga_i_c_commands [2020/12/14 20:30] – [0xB0-0xCF] Igor Yefmov |
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| ====== FX3 Host Vendor Command Reference ====== | ====== FX3 Host Vendor Command Reference ====== |
| | Please refer to [[code::fx3_vr_cmd|Vendor Request Commands' reference]] page for details. |
| |
| The following tables provide information on how to access the camera's functionality for ''FX3 Host Vendor Command Interface''. The address space is split into smaller chunks, grouped by common functionality: | The following tables provide information on how to access the camera's functionality for ''FX3 Host Vendor Command Interface''. The address space is split into smaller chunks, grouped by common functionality: |
| |''0'' Config not busy|Set to ''1'' while the config is not busy| | |''0'' Config not busy|Set to ''1'' while the config is not busy| |
| |
| ===== 0xB0-0xCF ===== | ===== 0xB0-0xCF - Color Correction Matrix (a.k.a. CCM or CMX) ===== |
| | Color Correction Matrix is often used as an "add-on" matrix during YUV->RGB conversion. In our case, since the de-bayering and RGB->YUV conversions happen literally on opposite sides of the imaging pipeline, we only use the portion of the corrections designed to compensate for the sensor's cross-talk, converting pre-debayer values \(R_0, Gr_0, Gb_0, B_0\) into \(R, Gr, Gb, B\) that are then used for conversion into RGB: |
| | |
| | \( |
| | \begin{bmatrix} R & Gr & Gb & B\end{bmatrix} |
| | = |
| | \begin{bmatrix} |
| | c_00 & c_01 & c_02 & c_03 \\ |
| | c_10 & c_11 & c_12 & c_13 \\ |
| | c_20 & c_21 & c_22 & c_23 \\ |
| | c_30 & c_31 & c_32 & c_33 |
| | \end{bmatrix} |
| | \cdot |
| | \begin{bmatrix} |
| | R_0 \\ |
| | Gr_0 \\ |
| | Gb_0 \\ |
| | B_0 |
| | \end{bmatrix} |
| | \) |
| ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ | ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ |
| |Reserved|''0xB0''-''0xCF''| | | | | | | | |Reserved|''0xB0''-''0xCF''| | | | | | | |
| |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| | |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| |
| |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| | |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| |
| |:::|:::|:::|''6'' Reserved| | | |:::|:::|:::|''6'' on-board fan| (FPGA-72+) ''1'' turns the on-board fan on, ''0'' turns it off | |
| |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| | |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| |
| |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | | |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | |
