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code:fx3_api [2024/06/08 03:43] – [Color gains] Igor Yefmovcode:fx3_api [2024/07/19 06:11] (current) – [Sysinfo] Igor Yefmov
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 ===== I²C access ===== ===== I²C access =====
 ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^
-|:!: FPGA I²C Bridge|''0xA4''|FPGA register offset|FPGA data (write)|R/W|\(0\) or \(1\)|[\(7:0\)] - FPGA data| **DEPRECATED in Gen5+** - use the ''Generic I²C access'' instead\\ **Up to Gen4** - FPGA write returns 0 byte buffer, FPGA read returns 1 byte buffer. Read/write is requested via control endpoint's direction attribute being set to ''DIR_FROM_DEVICE''/''DIR_TO_DEVICE''.\\ For details on individual commands refer to [[fpga_registers_map|FPGA I²C bridge]]| +|FPGA I²C Bridge|''0xA4''|FPGA register offset|FPGA data (write)|R/W|\(0\) or \(1\)|[\(7:0\)] - FPGA data| **DEPRECATED in Gen5+** - use the ''Generic I²C access'' instead\\ **Up to Gen4** - FPGA write returns 0 byte buffer, FPGA read returns 1 byte buffer. Read/write is requested via control endpoint's direction attribute being set to ''DIR_FROM_DEVICE''/''DIR_TO_DEVICE''.\\ For details on individual commands refer to [[fpga_registers_map|FPGA I²C bridge]]| 
-|:!: Sensor I²C bridge (\(8\)-bit configuration registers)|''0xA5''| [\(15:0\)] - sensor ''register'' address | ''mask'' and ''data'' (if writing) - see Notes column for details |R/W|\(0\) or \(1\)| [\(7:0\)] - sensor register's data | ''register'' - a \(16\) bit register address\\ ''mask'' - an \(8\)-bit MSB that specifies which bits to affect during a write operation - only the bits that are set in ''mask'' will be affected by bits in ''data''. Setting ''mask'' to \(0\) ultimately turns a write operation into a read one as no bits are getting modified\\ ''data'' - an \(8\)-bit LSB that specifies the new data to write into sensor's register. The write only affects the bits that are set in ''mask''\\ Read operation returns an \(8\)-bit register's value\\ Read/write is requested via control endpoint's direction attribute being set to ''DIR_FROM_DEVICE''/''DIR_TO_DEVICE''.\\ For details on each sensor's register's function refer to the sensor's specification | +|Sensor I²C bridge (\(8\)-bit configuration registers)|''0xA5''| [\(15:0\)] - sensor ''register'' address | ''mask'' and ''data'' (if writing) - see Notes column for details |R/W|\(0\) or \(1\)| [\(7:0\)] - sensor register's data | ''register'' - a \(16\) bit register address\\ ''mask'' - an \(8\)-bit MSB that specifies which bits to affect during a write operation - only the bits that are set in ''mask'' will be affected by bits in ''data''. Setting ''mask'' to \(0\) ultimately turns a write operation into a read one as no bits are getting modified\\ ''data'' - an \(8\)-bit LSB that specifies the new data to write into sensor's register. The write only affects the bits that are set in ''mask''\\ Read operation returns an \(8\)-bit register's value\\ Read/write is requested via control endpoint's direction attribute being set to ''DIR_FROM_DEVICE''/''DIR_TO_DEVICE''.\\ For details on each sensor's register's function refer to the sensor's specification | 
-|:!: Generic I²C access|''0xA6''|[\(15:8\)] \(8\)-bit I²C bus address\\ [\(7:6\)] [[#Generic I²C command selector|command selector]]\\ [\(5:3\)] [[#Generic I²C width selector|data width selector]]\\ [''2:0''] [[#Generic I²C width selector|address width selector]]|[\(7:0\)] - number of data elements to read/write|R/W| | |single/bulk read/write to/from an arbitrary device on I²C bus, supports \(8\), \(16\), \(32\) bit addressing and same for data OR poll for status or get result of a bulk I2C operation, see [[#Generic I²C access details|next section]] for details|+|Generic I²C access|''0xA6''|[\(15:8\)] \(8\)-bit I²C bus address\\ [\(7:6\)] [[#Generic I²C command selector|command selector]]\\ [\(5:3\)] [[#Generic I²C width selector|data width selector]]\\ [''2:0''] [[#Generic I²C width selector|address width selector]]|[\(7:0\)] - number of data elements to read/write|R/W| | |single/bulk read/write to/from an arbitrary device on I²C bus, supports \(8\), \(16\), \(32\) bit addressing and same for data OR poll for status or get result of a bulk I2C operation, see [[#Generic I²C access details|next section]] for details|
  
 ==== Generic I²C access details ==== ==== Generic I²C access details ====
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 ===== Sysinfo ===== ===== Sysinfo =====
 ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^
-|:!: Sysinfo|''0xA8''|data structure version:\\ <del>\(1\) - deprecated</del>\\ \(2\) - supported version | bitmask of additional checks to perform:\\ :!: \(0\) - reinit FPGA and/or sensor if needed\\ \(1\)-\(7\): reserved |R/O|\(54\)| <code>struct SysInfoV2</code> |Get various internal system info on the guts of the RTOS and the firmware running on FX3, as well as overall configuration and health check results. Returned bytes:\\ **Version 2**: [[SysInfoV2]] |+|:!: Sysinfo|''0xA8''|data structure version:\\ <del>\(1\) - deprecated</del>\\ \(2\) - supported version | bitmask of additional checks to perform:\\ :!: \(0\) - reinit FPGA and/or sensor if needed\\ \(1\)-\(7\): reserved |R/O|\(54\)| <code>struct SysInfoV2</code> |Get various internal system info on the guts of the RTOS and the firmware running on FX3, as well as overall configuration and health check results. Returned bytes: [[SysInfoV2]] |
 |Reserved|''0xA9''| | | | | | | |Reserved|''0xA9''| | | | | | |
  
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 ===== FPS control ===== ===== FPS control =====
 ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^
-|:!: FPS|''0xB0''| | |R/W|\(4\)|float32 FPS|FPS value is in IEEE float32 format, x86 LE|+|:!: FPS|''0xB0''| | |R/W|\(4\)|float32 FPS|FPS value is in IEEE 754 float32 format, x86 LE|
  
 ===== Bulk color grading ===== ===== Bulk color grading =====
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 See [[isp:ccm|Color correction matrix]] article in this Wiki's ISP section for more details. See [[isp:ccm|Color correction matrix]] article in this Wiki's ISP section for more details.
 ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^ ^Name ^Offset ^wIndex ^wValue ^Access type ^Byte length ^Return buffer bits ^Notes ^
-|:!: Color correction matrix|''0xB2''| ''0'' | ''0x0303'' |R/W|32|packed C-array <code>float[3][3]</code>|That data buffer could also be defined as <code>float[9]</code> or as <code>byte[sizeof(float) * 9]</code> for the same exact memory layout on LE systems|+|Color correction matrix|''0xB2''| ''0'' | ''0x0303'' |R/W|32|packed C-array <code>float[3][3]</code>|That data buffer could also be defined as <code>float[9]</code> or as <code>byte[sizeof(float) * 9]</code> for the same exact memory layout on LE systems|
  
 ===== Color gains ===== ===== Color gains =====
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 where \({black \space level}\) and \(Add\)itive values are unsigned 12-bit integers in range \([0..4095]\) and \(Mult\)iplicative coefficient is a 16-bit IEEE 754 ''float''ing point number in range \((0..8)\) (exclusive on both ends). where \({black \space level}\) and \(Add\)itive values are unsigned 12-bit integers in range \([0..4095]\) and \(Mult\)iplicative coefficient is a 16-bit IEEE 754 ''float''ing point number in range \((0..8)\) (exclusive on both ends).
 ^Name ^Offset ^wIndex ^wValue ^Access type ^Notes ^ ^Name ^Offset ^wIndex ^wValue ^Access type ^Notes ^
-|color gains|''0xB4''| MSB: reserved, must be ''0''\\ LSB: see [[#Color gain selector|color gain selector]] table |  ''0''  | R/W | read/write individual pre-debayer RGGB color gain triplet of coefficients, represented by a C-struct<code c++>struct ColorGain final{+|color gains|''0xB3''| MSB: reserved, must be ''0''\\ LSB: see [[#Color gain selector|color gain selector]] table |  ''0''  | R/W | read/write individual pre-debayer RGGB color gain triplet of coefficients, represented by a C-struct<code c++>struct ColorGain final{
   uint16_t bl;  // black level   uint16_t bl;  // black level
   uint16_t add; // additive   uint16_t add; // additive

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