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--- code:fpga_registers_map [2024/02/17 15:10] – created Igor Yefmov
+++ code:fpga_registers_map [2024/02/17 15:16] (current) – Igor Yefmov
@@ Line 1: / Line 1: @@
-The FPGA register maps are defined differently for [[fpga_map_gen3_and_4|Gen 3 and 4]] and for [[fpga_map_gen5|Gen 5]] cameras
+To control FPGA's functionality a whole lot of registers are defined which are accessible via I2C bus but the method differs drastically in address/data width. Both Xilinx-based Gen 3 and Gen 4 FPGAs are using 8-bit address and data whereas Gen 5 is using Intel's Avalon bus which is based on 32 bit address and data. The FPGA register maps are defined in these specs:
+   - [[fpga_map_gen3_and_4|Gen 3 and 4]]
+   - [[fpga_map_gen5|Gen 5]]
+The registers' maps between different version of cameras should be treated as incompatible.

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