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| code:fpga_map_gen5 [2026/06/11 02:19] – [Video output formats] Igor Yefmov | code:fpga_map_gen5 [2026/06/11 08:44] (current) – [Green Screen enhancer] Igor Yefmov |
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| The address space is broken down into smaller chunks, grouped by common functionality: | The address space is broken down into smaller chunks, grouped by common functionality: |
| ===== FPGA basic status and controls ===== | ===== FPGA basic status and controls ===== |
| ^ FPGA basic status and controls ^^^^^^ | ^ FPGA basic status and controls ^^^^^^ |
| ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^ | ^Address ^Name ^Bytes ^Access ^Bit mapping ^Notes ^ |
| |''0x5000'0000''|FPGA Version| 4 |R/O| see [[code#firmware_version_info|Firmware Version Info]] | | | |''0x5000'0000''|FPGA Version| 4 |R/O|see [[code#firmware_version_info|Firmware Version Info]]| | |
| |''0x5000'0004''|:!: FPGA status| 4 |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' DPC done\\ ''0'' SFP active| The bytes of the FPGA status register are allocated according to the little-ending memory layout of the following C-style declaration((For details on ''spi_config_status'' see [[code:code#FPGA config status - SPI codes|SPI codes]])):\\ <code c++> | |''0x5000'0004''|:!: FPGA status| 4 |R/O|see Notes for more details\\ \\ ''31:16'' [[code:code#FPGA config status - SPI codes|SPI codes]]\\ ''15:8'' FPGA core temperature\\ ''7:2'' reserved\\ ''1'' HDMI connected\\ ''0'' SFP+ active|The bytes of the FPGA status register are allocated according to the little-endian memory layout of the following C-style declaration((For details on ''spi_config_status'' see [[code:code#FPGA config status - SPI codes|SPI codes]])):\\ <code c++> |
| struct FpgaStatus{ | struct FpgaStatus{ |
| struct State{ | struct State{ |
| // there is an active device in SFP+ cage | // SFP+ module is present, has signal, and reports no fault |
| bool sfp_active:1; | bool sfp_active:1; |
| // DPC calibration is completed | |
| bool dpc_done:1; | // HDMI sink is connected and detected through HPD |
| // reading of the FPGA's internal temperature sensor in degrees of Fahrenheits | bool hdmi_connected:1; |
| uint8_t reserved:6; | uint8_t reserved:6; |
| } state; | } state; |
| | |
| uint8_t core_temperature; | uint8_t core_temperature; |
| uint16_t spi_config_status; | uint16_t spi_config_status; |
| };</code> | | };</code>| |
| ===== FPGA operation mode ===== | ===== FPGA operation mode ===== |
| ^ FPGA operation mode((Set the operation mode of the FPGA (e.g. switch into firmware programming) and enable/disable individual media output channels and specific transformation blocks)) ^^^^^^ | ^ FPGA operation mode((Set the operation mode of the FPGA (e.g. switch into firmware programming) and enable/disable individual media output channels and specific transformation blocks)) ^^^^^^ |
| ==== Video output formats ==== | ==== Video output formats ==== |
| ^Name ^Address ^Access ^Bit mapping ^Notes ^ | ^Name ^Address ^Access ^Bit mapping ^Notes ^ |
| |:!: Video output format|''0x5000'0700''|R/W|:!: ''7:4'' - UVC\\ :!: ''3:0'' - FPS code for SDI, SFP+, SDI|Bit depth for all video formats is set in register ''0x49''\\ UVC video formats:\\ :!:''0'' - "RAW" greyscale pre-debayer pixels\\ :!:''1'' - 4:4:4 RGB\\ :!:''2'' - (res) packed YCbCr 4:4:4\\ :!:''3'' - packed YCbCr 4:2:2\\ :!:''4'' - (res) packed YCbCr 4:2:0\\ :!:''5'' - (res) planar YCbCr 4:4:4\\ :!:''6'' - (res) planar YCbCr 4:2:2\\ :!:''7'' - planar YCbCr 4:2:0\\ :!:''8-15'' - (res) MJPEG, MPEG-x/H.26x, etc\\ \\ SDI/HDMI and SFP+ video output formats/FPS are always in unison. See [[code:fx3_hvci_and_fpga_i_c_commands#sdi_fps|SDI FPS]] table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format| | |:!: Video output format and pixel bit depth|''0x5000'0700''|R/W|''31:16'' - reserved\\ :!: ''15:12'' - UVC\\ :!: ''11:8'' - FPS code for SDI, SFP+, SDI|Bit depth for all video formats is set in register ''0x5000'0708''\\ UVC video formats:\\ :!:''0'' - "RAW" greyscale pre-debayer pixels\\ :!:''1'' - 4:4:4 RGB\\ :!:''2'' - (res) packed YCbCr 4:4:4\\ :!:''3'' - packed YCbCr 4:2:2\\ :!:''4'' - (res) packed YCbCr 4:2:0\\ :!:''5'' - (res) planar YCbCr 4:4:4\\ :!:''6'' - (res) planar YCbCr 4:2:2\\ :!:''7'' - planar YCbCr 4:2:0\\ :!:''8-15'' - (res) MJPEG, MPEG-x/H.26x, etc\\ \\ SDI/HDMI and SFP+ video output formats/FPS are always in unison. See [[code:fx3_hvci_and_fpga_i_c_commands#sdi_fps|SDI FPS]] table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format| |
| |:!: Video output pixel bit depth|''0x5000'0708''|R/W|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit values:\\ ''0'' => 8\\ ''1'' => 10\\ ''2'' => 12\\ ''3'' => 14\\ Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC currently **only** supports ''8''-bit color depth| | |:::|:::|:::|:!: ''7:6'' - HDMI\\ :!: ''5:4'' - SDI\\ :!: ''3:2'' - SFP+\\ :!: ''1:0'' - UVC|Pixel bit values:\\ ''0'' => 8\\ ''1'' => 10\\ ''2'' => 12\\ ''3'' => 14\\ Not all values are valid, for example SDI and SFP+ both do not support ''8''-bit output and UVC currently **only** supports ''8''-bit color depth| |
| | |:!: Video output geometry|''0x5000'0708''|R/W|:!: ''31:16'' - uint16_t horizontal\\ :!: ''15:0'' - uint16_t vetical|Horizontal x vertical resolution, in pixels| |
| |
| ==== FOURCC formats (for UVC) ==== | ==== FOURCC formats (for UVC) ==== |
| | ''0x0C'' (120) | 297 | 1188 | | | | ''0x0C'' (120) | 297 | 1188 | | |
| |
| | |
| | ==== Video pipeline setup ==== |
| | ^Name ^Address ^Access ^Bit mapping ^Notes ^ |
| | |:!: Initial scaler setup|''0x5000'0800''|R/W|''31:4'' - reserved\\ :!: ''3:2'' - scale divisor\\ :!: ''1:0'' - filter mode|The initial scaler is the first post-debayer pipeline stage. Horizontal and vertical scaling always use the same divisor, preserving the input aspect ratio.\\ \\ Scale divisor values:\\ ''0'' - 1:1 (pass-through)\\ ''1'' - 2:1 (output width and height are each half of the input)\\ ''2-3'' - reserved\\ \\ Filter mode values:\\ ''0'' - nearest (select the top-left pixel from each source region)\\ ''1'' - box average\\ ''2-3'' - reserved for future filters\\ \\ The filter mode is ignored in 1:1 pass-through mode. This register must only be changed while the video pipeline is fully stopped.| |
| | |:!: UVC scaler output geometry|''0x5000'0804''|R/W|:!: ''31:16'' - uint16_t horizontal\\ :!: ''15:0'' - uint16_t vertical|Requested UVC scaler output resolution, in pixels. The input geometry is derived internally from the output of the initial scaler and is not independently configurable.\\ \\ Setting the output geometry equal to the input geometry selects 1:1 pass-through. Initially, only downscaling is supported. The requested width and height must be non-zero and must not exceed the input geometry. Packed YCbCr 4:2:2 output requires an even horizontal resolution. This register must only be changed while UVC output is stopped.| |
| | |:!: UVC scaler control|''0x5000'0808''|R/W|''31:2'' - reserved\\ :!: ''1:0'' - filter mode|Filter mode values:\\ ''0'' - nearest\\ ''1'' - box average\\ ''2-3'' - reserved for future filters\\ \\ Horizontal and vertical sampling ratios are derived internally from the initial scaler output geometry and requested UVC output geometry. This register must only be changed while UVC output is stopped.| |
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| ===== Green Screen enhancer ===== | ===== Green Screen enhancer ===== |
