The following tables provide information on how to access the camera's functionality for an FPGA I²C bridge.
Here's a sample code (skipping all error checking) that sets the LED to bright-yellow color:
S2R::FX3 dev; // auto-open device #0 using S2R::FX3; dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 255, 0x08); // red dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 255, 0x0A); // green dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 0, 0x0C); // blue
The address space is broken down into smaller chunks, grouped by common functionality:
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
FPGA Version #0 | 0x00 | R/O | 7:5 Vendor ID4:0 HW_CFG_ID | |
FPGA Version #1 | 0x01 | R/O | 7:0 Product ID | |
FPGA Version #2 | 0x02 | R/O | 7:3 Release type2:0 Build number MSB | Build number is split into 2 MSB and 8 LSB for a combined total width of 10 bits |
FPGA Version #3 | 0x03 | R/O | 7:0 Build number LSB |
|
FPGA config status #0 | 0x04 | R/O | see SPI codes for details | LSB (bits 7 -0 ) of the FPGA config status |
FPGA config status #1 | 0x05 | R/O | see SPI codes for details | MSB (bits 15 -8 ) of the FPGA config status |
FPGA control | 0x06 | R/W | Global control of the FPGA's functionality | |
7 FPGA config enable | If bit 7 is set, the GPIF becomes read only and waits for an update bitstream |
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6 on-board fan | (FPGA-72+) 1 turns the on-board fan on, 0 turns it off |
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5 RAW Mode | Setting bit 5 and clearing bit 0x06::2 will enable RAW mode output (4K Only) |
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4 Video Format | Bit 4 selects between NV12 ('1') and YUY2 ('0') output formats |
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3 DPC enable | Setting bit 3 along with bit 0x06::0 will perform a DPC correction |
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2 | 2 is to enable/disable Horizontal Subsampling |
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1 Audio enable | Bit 1 is to enable/disable on-board microphones |
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0 Video enable | Bit 0 enables/disables video streaming |
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FPGA core temperature | 0x07 | R/O | 7:0 - temperature in Farenheits | Reading of the FPGA's internal temperature sensor in degrees of Farenheits |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
LED_RED_L | 0x08 | R/W | 7:0 Red LED | LSB of LED's red intensity in range [0..255] |
LED_RED_H | 0x09 | R/W | Reserved | |
LED_GREEN_L | 0x0A | R/W | 7:0 Green LED | LSB of LED's green intensity in range [0..255] |
LED_GREEN_H | 0x0B | R/W | Reserved | |
LED_BLUE_L | 0x0C | R/W | 7:0 Blue LED | LSB of LED's blue intensity in range [0..255] |
LED_BLUE_H | 0x0D | R/W | Reserved |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Chroma NR Control | 0x0E | R/W | 7 Reserved, must be 0 6:0 value | Chroma (color or an \(H\) component of the \(H/S/L\) pixel data) noise reduction in range \([0\%..100\%]\) mapped into \([0..127]\). Setting this to 0 effectively turns the chroma denoising off |
Luma NR Control | 0x0F | R/W | 7 Reserved, must be 0 6:0 value | Luma (brightness or an \(L\) component of the \(H/S/L\) pixel data) noise reduction in range \([0\%..100\%]\) mapped into \([0..127]\). Setting this to 0 effectively turns the luma denoising off |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Brightness_L | 0x10 | R/W | 7:0 LSB | 16 bits of brightness are split into 8 bits of LSB and MSB |
Brightness_H | 0x11 | R/W | 7:0 MSB |
|
Contrast_L | 0x12 | R/W | 7:0 LSB | 16 bits of contrast are split into 8 bits of LSB and MSB |
Contrast_H | 0x13 | R/W | 7:0 MSB |
|
Saturation_L | 0x14 | R/W | 7:0 LSB | 16 bits of saturation are split into 8 bits of LSB and MSB |
Saturation_H | 0x15 | R/W | 7:0 MSB |
|
Sharpness_L | 0x16 | R/W | 7:0 LSB | 16 bits of sharpness are split into 8 bits of LSB and MSB |
Sharpness_H | 0x17 | R/W | 7:0 MSB |
|
Gamma_L | 0x18 | R/W | 7:0 LSB | 16 bits of gamma are split into 8 bits of LSB and MSB |
Gamma_H | 0x19 | R/W | 7:0 MSB |
|
Hue_L | 0x1A | R/W | 7:0 LSB | 16 bits of hue are split into 8 bits of LSB and MSB |
Hue_H | 0x1B | R/W | 7:0 MSB |
|
Reserved | 0x1C | |||
Reserved | 0x1D | |||
Reserved | 0x1E | |||
Reserved | 0x1F |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
DPC Threshold LSB | 0x20 | R/W | 7:0 LSB | 16 bit of DPC Threshold are split into 8 bits of LSB and MSB |
DPC Threshold MSB | 0x21 | R/W | 7:0 MSB |
|
DPC count LSB | 0x22 | R/O | 7:0 LSB | Once the DPC calibration is done the 16-bit value is stored in these 2 registers |
DPC count MSB | 0x23 | R/O | 7:0 MSB |
|
Grey threshold | 0x24 | R/W | 7:0 | If the full range of incoming \(R,G,B\) triplet is up to that number (inclusive), force both the \(H\) and \(S\) to be 0 |
Reserved | 0x25 | |||
Reserved | 0x26 | |||
Reserved | 0x27 |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Y average | 0x28 | R/O | 7:0 value | |
flags | 0x29 | R/O | 7:0 value | flags for OverExposure and SFP+ cage device. The following bits are currently defined:7:3 - reserved2 - set to 1 if there is an active device in SFP+ cage 1)1 - indicates whether a red overexposure is detected0 - set if there is a general overexposure detected |
FPS_L | 0x2B | R/O | 7:0 LSB | 16-bit unsigned value representing number of 10μs units between frame start signals from the image sensor, e.g. a value of 1000 means it took 10ms between 2 frame start signals, which corresponds to 100FPS |
FPS_H | 0x2C | R/O | 7:0 MSB |
|
Reserved | 0x2D | |||
AWB Y limit | 0x2E | R/W | 7:0 value | Lower bound brightness threshold for pixels to qualify for AWB statistic counter, default value 100 |
AWB S limit | 0x2F | R/W | 7:0 value | Upper bound saturation threshold for pixels to qualify for AWB statistic counter, default value 10 |
Reserved | 0x30 | |||
AWB Red total counter | 0x33-0x31 | R/O | 24-bit value | 0x33 is MSB, 0x31 is LSB |
Reserved | 0x34 | |||
AWB Green total counter | 0x37-0x35 | R/O | 24-bit value | 0x37 is MSB, 0x35 is LSB |
Reserved | 0x38 | |||
AWB Blue total counter | 0x3B-0x39 | R/O | 24-bit value | 0x39 is MSB, 0x3B is LSB |
AWB total pixel counter | 0x3F-0x3C | R/O | 32-bit value | 0x3F is MSB, 0x3C is LSB |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
AWB Red adjustment | 0x40 | R/W | 7:0 - value | a signed 8-bit value of an adjustment to apply to every pixel in Red channel. Default is 0 |
reserved | 0x41 | |||
AWB Green adjustment | 0x42 | R/W | 7:0 - value | a signed 8-bit value of an adjustment to apply to every pixel in Green channel. Default is 0 |
reserved | 0x43 | |||
AWB Blue adjustment | 0x44 | R/W | 7:0 - value | a signed 8-bit value of an adjustment to apply to every pixel in Blue channel. Default is 0 |
reserved | 0x45 |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Media output modules | 0x46 | R/W | 7 - res6 - res (headphones)5 - res (UAC)4 - res3 - res2 - SDI video1 - SFP+ video0 - UVC | Enable/disable state of individual media output modules for video and audio streams |
Video transform blocks | 0x47 | R/W | 7 - res (sharpness)6 - res5 - res4 - res3 - res2 - HSL pipeline1 - CCM0 - res (UVC Gamma) | Enable/disable individual transformation blocks in video pipeline |
Video output format | 0x48 | R/W | 7:4 - UVC3:0 - SDI FPS | Bit depth for all video formats is set in register 0x49 UVC video formats: 0 - “RAW” greyscale pre-debayer pixels1 - 4:4:4 RGB2 - (res) packed YCbCr 4:4:43 - packed YCbCr 4:2:24 - (res) packed YCbCr 4:2:05 - (res) planar YCbCr 4:4:46 - (res) planar YCbCr 4:2:27 - planar YCbCr 4:2:08-15 - (res) MJPEG, MPEG-x/H.26x, etcSDI and SFP+ video output formats/FPS are always in unison. See SDI FPS table below for codes. SDI output is always in a packed (not planar) YUV 4:2:2 format |
Video output pixel bit depth | 0x49 | R/W | 7:6 - res5:4 - SDI3:2 - SFP+1:0 - UVC | Pixel bit depths \(d_p\) is calculated from a 2-bit value \(N\) as: \[d_p = (N+4)*2\] Not all values are valid, for example SDI and SFP+ both do not support 8 -bit output and UVC only supports 8 -bit color depth, at least for now |
MIPI configuration | 0x4A | R/W | 7:4 - res3:2 - de-mosaicing strategy1:0 - MIPI bit depth | De-mosaicing strategy directs the use of a specific implementation of color reconstruction:3 , 2 - reserved1 - use “branching 5×5”, for example the one described here0 - use “branchless 5×5”, like the one described in hereMIPI bit depth controls the data packing format for the pixels coming through MIPI interface. MIPI bit depth \(d_p\) is calculated from a 2-bit value \(N\) as: \[d_p = (N+4)*2\] |
Reserved | 0x4B | |||
Audio transform blocks | 0x4C | R/W | 7:0 - res | Enable/disable individual transformation blocks in audio pipeline |
Reserved | 0x4D | |||
Reserved | 0x4E | |||
Reserved | 0x4F |
A combination of data in 0x49[1:0]
(pixel bit depth) and 0x48[6:3]
(video format) used for UVC is mapped into standard FOURCC codes as summarized in the following table:
0x49[1:0] \0x48[6:3] | 0 (RAW) | 1 (RGB) | 2 (packed YUV 4:4:42)) | 3 (packed YUV 4:2:23)) | 7 (planar YUV 4:2:04)) |
---|---|---|---|---|---|
0 (8 bit) | BA81/BYR1/GREY/Y8/Y800 (8bpp) | BI_RGB/RGB (24bpp) | Y444/IYU2 (24bpp) | YUY2/YUYV (16 bpp) | NV12 (12bpp) |
1 (10 bit) | Y105) (16bpp6)) | BI_BITFIELDS (48bpp) | Y410 (32bpp7)) | Y210 (32bpp) YUVP?/Y42T (24bpp?) | P010 (32bpp) |
2 (12 bit) | BYR2 (16pbb8)) | BI_BITFIELDS (48bpp) | Y4129) (40bpp10)) | Y21211) (32bpp12)) | P01213) (32bpp14)) |
3 (14 bit) | Y1615) (16bpp16)) | BI_BITFIELDS (48bpp) | Y41417) (48bpp18)) | Y21419) (32bpp20)) | P01421) (32bpp22)) |
Below is the table that lists codes for supported SDI FPS settings st in 0x48[3:0]
:
FPS | code |
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23.98 | 0x01 |
24 | 0x02 |
25 | 0x04 |
29.97 | 0x05 |
30 | 0x06 |
50 | 0x08 |
59.94 | 0x09 |
60 | 0x0A |
120 | 0x0C |
Frame geometry | MHz | FPS |
---|---|---|
1920×1080 | 74.18 | 23.98 |
29.97 | ||
74.25 | 24 | |
25 | ||
30 | ||
148.35 | 59.94 | |
148.5 | 50 | |
60 | ||
297 | 120 | |
3840×2160 | 296.70 | 23.98 |
29.97 | ||
297 | 24 | |
25 | ||
30 | ||
593.41 | 59.94 | |
594 | 50 | |
60 | ||
1188 | 120 | |
7680×4320 | 1188 | 24 |
30 |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Reserved | 0x50 -0x5F |
Name | Offset | Access | Bit mapping | Notes |
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Reserved | 0x60 -0x6F |
Name | Offset | Access | Bit mapping | Notes |
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Reserved | 0x70 -0x7F |
“Green screen”, a.k.a. “Chroma Key” on-board optimization is designed to replace a range of colors with a single solid one
If enabled these setting take precedence over other 3 bands
Name | Offset | Access | Bit mapping | Notes |
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CK control | 0x80 | R/W | 7:1 reserved0 enable | enable/disable Chroma Key control |
CK status | 0x81 | reserved | ||
CK saturation min | 0x82 | R/W | 7:0 sat. min | [0..255] to specify the minimum saturation threshold |
CK saturation max | 0x83 | R/W | 7:0 sat. max | [0..255] to specify the maximum saturation threshold |
CK luma min | 0x84 | R/W | 7:0 luma min | [0..255] to specify the minimum brightness threshold |
CK luma max | 0x85 | R/W | 7:0 luma max | [0..255] to specify the maximum brightness threshold |
CK hue LSB | 0x86 | R/W | 7:0 hue LSB | 14 bits of a signed hue value are split into 8 LSB and 6 MSB, its [-8K..+8K] range is mapped into [-180°..+180°] |
CK hue MSB | 0x87 | R/W | 7:6 reserved5:0 hue MSB |
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CK tolerance LSB | 0x88 | R/W | 7:0 tolerance LSB | 13 bits of an unsigned hue tolerance value are split into 8 LSB and 5 MSB, valid range is [0..8K], which is mapped into [0°..180°]. That value specifies how far to stretch the CK hue value both ways (symmetrically). If the CK tolerance is above 90° the covered color space is over 50% of values |
CK tolerance MSB | 0x89 | R/W | 7:5 reserved4:0 tolerance MSB |
|
CK red LSB | 0x8A | R/W | 7:0 red LSB | |
CK red MSB | 0x8B | R/W | reserved | |
CK green LSB | 0x8C | R/W | 7:0 green LSB | |
CK green MSB | 0x8D | R/W | reserved | |
CK blue LSB | 0x8E | R/W | 7:0 blue LSB | |
CK blue MSB | 0x8F | R/W | reserved |
Color substitution (if enabled) takes place after the first band had a chance to process the pixels
The layout of the settings is identical to that of band #0 just shifted down by a paragraph and occupying address block 0x90-0x9F
Color substitution (if enabled) takes place after the first and second bands had a chance to process the pixels
The layout of the settings is identical to that of band #0 just shifted down by 2 paragraphs and occupying address block 0xA0-0xAF
Color substitution (if enabled) takes place after other bands had a chance to process the pixels
The layout of the settings is identical to that of band #0 just shifted down by 3 paragraphs and occupying address block 0xB0-0xBF
Name | Offset | Access | Bit mapping | Notes |
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switch | 0xC0 | W | Controls what information is being read/written by accessing the next set of registers (0xC2..0xC3 ) |
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7:5 table switch | 000 - Hue vs. Hue (14 bits)001 - Hue vs. Saturation (12 bits )010 - Lightness vs. Saturation (12 bits)011 - Saturation vs. Saturation (12 bits)23)100 - Lightness vs. Lightness (12 bits)101 - Hue vs. Lightness (12 bits)24)110-111 - reserved |
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4:1 page | Reserved for a page number in the table, currently is always set to 0 |
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0 access mode | the only valid value right now is 0 , which is “normal mode”, in which all the subsequent access to the registers in this API block are governed by the values in 0xC0 and 0xC1 1 would be used for “bulk access” where after a read or write access to register 0xC2 the “Index” value will auto-increment by one so that the next pair will access the subsequent table slot |
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Index LSB | 0xC1 | W | 7:0 index LSB | index into a page in the table (we only use 6 bits today and the rest are ignored) |
Value L | 0xC2 | R/W | 7:0 LSB | 16 bits split into 8 LSB and 8 MSB - for a “Hue vs. Hue” table the 14 bits signed value is in range [-8192..+8192] which maps linearly into a Hue angle range -180°..+180° - for a “Hue vs. Saturation” table (as well as for similar tables LvS and SvS) the 12 bit unsigned value in range [0..+1280] maps linearly into a Saturation range [0%..1000%] where 100% is the neutral position and 0% produces a greyscale image- (until FPGA v.72) for a “Lightness vs. Lightness” table (as well as for similar table HvL) the 12 bit unsigned value in range [0..+4095] maps linearly into a Lightness absolute range [0..255] where 0 is pitch black and 255 is the maximum possible pixel luminosity value- (starting with FPGA v.73) for a “Lightness vs. Lightness” table (as well as for similar table HvL) the 13 bit signed value in range [-4096..+4095] maps linearly into a Lightness *relative* (adjustment) range [-256..255] where 0 is no adjustment to pixel luminosity value |
Value H | 0xC3 | R/W | 7:0 MSB |
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Reserved | 0xC4 -0xCF |
See Color correction matrix article in this Wiki's ISP section for more details. The 16-bit (MSB-LSB) value is defined as 7+9 bits, where MSB[7:1] are the integer part and MSB[0]LSB[7:0] is the fractional part (effectively that value is 512 times larger than the original fractional part).
Name | Offset | Access | Bit mapping | Notes |
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CCM_00_L | 0xD0 | R/W | 7:0 LSB | \(CCM_{00}\) |
CCM_00_H | 0xD1 | R/W | 7:0 MSB |
|
CCM_01_L | 0xD2 | R/W | 7:0 LSB | \(CCM_{01}\) |
CCM_01_H | 0xD3 | R/W | 7:0 MSB |
|
CCM_02_L | 0xD4 | R/W | 7:0 LSB | \(CCM_{02}\) |
CCM_02_H | 0xD5 | R/W | 7:0 MSB |
|
CCM_10_L | 0xD6 | R/W | 7:0 LSB | \(CCM_{10}\) |
CCM_10_H | 0xD7 | R/W | 7:0 MSB |
|
CCM_11_L | 0xD8 | R/W | 7:0 LSB | \(CCM_{11}\) |
CCM_11_H | 0xD9 | R/W | 7:0 MSB |
|
CCM_12_L | 0xDA | R/W | 7:0 LSB | \(CCM_{12}\) |
CCM_12_H | 0xDB | R/W | 7:0 MSB |
|
CCM_20_L | 0xDC | R/W | 7:0 LSB | \(CCM_{20}\) |
CCM_20_H | 0xDD | R/W | 7:0 MSB |
|
CCM_21_L | 0xDE | R/W | 7:0 LSB | \(CCM_{21}\) |
CCM_21_H | 0xDF | R/W | 7:0 MSB |
|
CCM_22_L | 0xE0 | R/W | 7:0 LSB | \(CCM_{22}\) |
CCM_22_H | 0xE1 | R/W | 7:0 MSB |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Reserved | 0xE2 | |||
Reserved | 0xE3 | |||
Reserved | 0xE4 | |||
Reserved | 0xE5 | |||
Reserved | 0xE6 | |||
Reserved | 0xE7 | |||
Reserved | 0xE8 | |||
Reserved | 0xE9 | |||
Reserved | 0xEA | |||
Reserved | 0xEB | |||
Reserved | 0xEC | |||
Reserved | 0xED | |||
Reserved | 0xEE | |||
Reserved | 0xEF |
Name | Offset | Access | Bit mapping | Notes |
---|---|---|---|---|
Reserved | 0xF0 | |||
Reserved | 0xF1 | |||
Reserved | 0xF2 | |||
Reserved | 0xF3 | |||
Reserved | 0xF4 | |||
Reserved | 0xF5 | |||
Reserved | 0xF6 | |||
Reserved | 0xF7 | |||
Reserved | 0xF8 | |||
Reserved | 0xF9 | |||
Reserved | 0xFA | |||
Reserved | 0xFB | |||
Reserved | 0xFC | |||
Reserved | 0xFD | |||
Reserved | 0xFE | |||
Reserved | 0xFF |