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| code:code [2024/04/01 04:21] – [Preface] Igor Yefmov | code:code [2024/04/02 08:38] – [Build number] Igor Yefmov |
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| Controlling the camera is done via writing "registers" - think of them as address locations. There are generally 4 ways to interface with the camera from a host: | Controlling the camera is done via writing "registers" - think of them as address locations. There are generally 4 ways to interface with the camera from a host: |
| - standard UVC - this one is automagically supported by any UVC 1.1 compliant OS, which in the year 2017 would be "any modern OS". This interface covers the universally standardized controls for [[https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/uvc-driver-implementation-checklist|USB Video Class]] | - [[https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/uvc-driver-implementation-checklist|standard UVC]] - this one is automagically supported by any UVC 1.1 compliant OS, which in the year 2017 would be "any modern OS". This interface covers the universally standardized controls for USB Video Class |
| - [[fx3_api|FX3 Host Vendor Command Interface]] - this interfaces with the Cypress's FX3 and is the primary [[fx3_api|FX3 API]] | - [[fx3_api|FX3 Host Vendor Command Interface]] - this interfaces with the Cypress's FX3 and is the primary [[fx3_api|FX3 API]] |
| - [[fpga_registers_map|FPGA I²C Access]] - a "window" into a host of additional commands that are performed on FPGA, this is highly dependent on the FPGA model used and camera's generation and is not exactly intended for direct use outside of developing FX3 APIs and during development cycle of GUI implementation. The FPGA register maps are defined [[fpga_registers_map|on this page]] | - [[fpga_registers_map|FPGA I²C Access]] - a "window" into a host of additional commands that are performed on FPGA, this is highly dependent on the FPGA model used and camera's generation and is not exactly intended for direct use outside of developing FX3 APIs and during development cycle of GUI implementation. The FPGA register maps are defined [[fpga_registers_map|on this page]] |
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| | Previous iterations had different bit layout for the Version Info, see details here: [[Firmware Versioning Evolution]] |
| ====== Firmware Versioning evolution ====== | ====== Firmware Versioning evolution ====== |
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