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code:code [2024/02/17 16:00] – [Hardware ID for %%VendorId%% 1 (Xylinx)] Igor Yefmov | code:code [2024/04/02 08:41] – Igor Yefmov | ||
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- | Controlling the camera is done via writing " | + | ====== Preface ====== |
- | - standard UVC - this one is automagically supported by any UVC 1.1 compliant OS, which in the year 2017 would be "any modern OS". This interface covers the universally standardized controls for [[https:// | + | |
- | - (Gen 3 and Gen 4) direct I²C access via Cypress' | + | |
- | - FX3 Host Vendor Command Interface - this interfaces with the Cypress' | + | |
- | - FPGA I²C Access - a " | + | |
- | The last two ([[code:fx3_hvci_and_fpga_i_c_commands# | + | Controlling the camera is done via writing " |
+ | - [[https:// | ||
+ | - [[fx3_api|FX3 Host Vendor Command Interface]] - this interfaces with the Cypress' | ||
+ | - [[fpga_registers_map|FPGA I²C Access]] - a " | ||
+ | - (Gen 3 and Gen 4) direct | ||
If you are set on writing your own UI and don't want to be bothered too much with figuring out how to communicate with the camera you have an option of using the [[code: | If you are set on writing your own UI and don't want to be bothered too much with figuring out how to communicate with the camera you have an option of using the [[code: | ||
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|3|Artix %%UltraScale+%% XCAU25P| | |3|Artix %%UltraScale+%% XCAU25P| | ||
- | ==== Hardware ID for %%VendorId%% 2 (Altera) | + | ==== Hardware ID for VendorId 2 (Altera) |
|Code |Value | | |Code |Value | | ||
|1|Cyclone 10 GX| | |1|Cyclone 10 GX| | ||
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|# | |# | ||
+ | |||
+ | ---- | ||
+ | Previous iterations had different bit layout for the Version Info, see details here: [[Firmware Versioning Evolution]] | ||
+ | ---- | ||
+ | ===== Vendor ID ===== | ||
+ | ^Code ^Value ^ | ||
+ | |1|Cypress| | ||
+ | |||
+ | ===== Hardware ID ===== | ||
+ | ^Code ^Value ^ | ||
+ | |1|FX3| | ||
+ | |||
+ | ===== Product ID ===== | ||
+ | ^Code ^Value ^ | ||
+ | |1|reserved for Gen 1 camera, a.k.a. "Moon landing" | ||
+ | |2|reserved for Gen 2 camera, a.k.a. " | ||
+ | |3|Gen 3 camera (Alpha), a.k.a. " | ||
+ | |4|Gen 3 camera, Production| | ||
+ | |5|Gen 4 camera, a.k.a. " | ||
+ | |6|Gen 5 camera, either " | ||
+ | |||
+ | ===== Release type ===== | ||
+ | ^ Code ^ Name ^ Meaning ^ | ||
+ | |0|Private build| Private build for debugging and similar purposes | | ||
+ | |1|Alpha| feature-incomplete early development cycle " | ||
+ | |2|Beta| feature-complete, | ||
+ | |3|Evaluation| Tech preview | | ||
+ | |4|Release candidate| feature complete and stable | | ||
+ | |5|Release| general availability | | ||
+ | |6|Backport| backport of a feature from next gen camera | | ||
+ | |7|Emergency bug fix| a critical post-release bugfix | | ||
+ | |||
+ | ===== Build number ===== | ||
+ | ^Code ^Value ^ | ||
+ | |# | ||
+ | |||
+ | |||
+ | ====== FPGA Version Info ====== | ||
+ | The version id is also encoded into the firmware image file name as: | ||
+ | < | ||
+ | |||
+ | |||
+ | ===== Vendor ID ===== | ||
+ | A '' | ||
+ | ^Code ^Value ^ | ||
+ | |1|Xilinx (AMD)| | ||
+ | |2|Altera (Intel)| | ||
+ | |||
+ | ===== Hardware ID ===== | ||
+ | A '' | ||
+ | ^%%VendorId%%^Code ^Value ^ | ||
+ | |1|1|Artix-7 100T| | ||
+ | |1|2|Artix-7 200T| | ||
+ | |1|3|Artix %%UltraScale+%% XCAU25P| | ||
+ | |2|1|Cyclone 10 GX| | ||
+ | ===== Product ID ===== | ||
+ | An '' | ||
+ | ^Code ^Value ^ | ||
+ | |1|reserved| | ||
+ | |2|reserved| | ||
+ | |3|Gen 3 camera (Alpha), a.k.a. " | ||
+ | |4|Gen 3 camera, Production| | ||
+ | |5|Gen 4 camera, a.k.a. “Vitreledonella”| | ||
+ | |6|Gen 5 camera, prosumer grade " | ||
+ | |7|Gen 5 camera, professional grade " | ||
+ | ===== Release type ===== | ||
+ | Lower '' | ||
+ | ^Code ^Value ^ | ||
+ | |0|Private build| | ||
+ | |1|Alpha| | ||
+ | |2|Beta| | ||
+ | |3|Eval/ | ||
+ | |4|Release candidate| | ||
+ | |5|Release| | ||
+ | |6|Backport| | ||
+ | |7|Emergency bug fix| | ||
+ | |||
+ | ===== Build number ===== | ||
+ | '' | ||
+ | ^Code ^Value ^ | ||
+ | |# | ||
+ | |||
+ | ====== FPGA config status - SPI codes ====== | ||
+ | These are the status bits that indicate the FPGA programming (reconfiguring) process: | ||
+ | ^ Bit name ^ Description ^ | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
+ | |'' | ||
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+ | |'' | ||
+ | |'' | ||