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| code:fx3_hvci_and_fpga_i_c_commands [2019/11/13 00:27] – [0xA8-0xA9 - sysinfo and debugging] Igor Yefmov | code:fx3_hvci_and_fpga_i_c_commands [2020/04/12 12:59] – [0x00-0x07 - FPGA general access] Igor Yefmov |
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| |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| | |FPGA control|''0x06''|R/W| |Global control of the FPGA's functionality| |
| |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| | |:::|:::|:::|''7'' FPGA config enable|If bit ''7'' is set, the GPIF becomes read only and waits for an update bitstream| |
| |:::|:::|:::|''6'' Reserved| | | |:::|:::|:::|''6'' on-board fan| (FPGA-72+) ''1'' turns the on-board fan on, ''0'' turns it off | |
| |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| | |:::|:::|:::|''5'' RAW Mode|Setting bit ''5'' and clearing bit ''0x06::2'' will enable RAW mode output (4K Only)| |
| |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | | |:::|:::|:::|''4'' Video Format|Bit ''4'' selects between NV12 ('1') and YUY2 ('0') output formats | |
