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code:fx3_hvci_and_fpga_i_c_commands

Preface

SUB2r camera is built on a Cypress FX3 chipset that facilitates the Super-Speed USB 3.0+ communication between the device and a host system. Every component of the camera, be it an FPGA or an image sensor, receives user commands via that Cypress FX3.

On Windows the device is registered with a GUID {36FC9E60-C465-11CF-8056-444553540000} and if you are not planning on using the SUB2r-lib for your development - that would be the GUID to search for to properly connect to the command channel.

Whether you use SUB2r-lib or not you need to install the provided driver for the OS to properly configure the device in order to be able to connect to its control endpoints.

Here's a sample code that shows how to send commands to both the FX3 Host and to FPGA I²C bridge. The code lacks error checking (for clarity) and this should go without saying that if you copy-paste it into your code you must add error handling :)

// set a new auto-functions' update interval to 2x the default
// just issue the command directly to FX3's vendor request interface
void setUUInterval(){
    S2R::I2C fx3;
    fx3.open(0);
    fx3.vrCmd(0xDF, S2R::FX3::write, 6000, 0);
}
 
// run DPC calibration - also just a straight-up vendor request command to FX3
void runDPC(UCHAR _threshold = 240){
    S2R::I2C fx3;
    fx3.open(0);
    fx3.vrCmd(S2R::FX3::calibrate_dpc, S2R::FX3::write, _threshold, 0);
}
 
// increase LED's green brightness by 25%
// utilize the FPGA's I²C bridge
void lightUpTheGreen()
{
    using Cmd = S2R::FX3::Fx3Cmd;
    using OpType = S2R::FX3::VrCmdOpType;
 
    S2R::FX3 fx3;   // `S2R::I2C fx3;` works as well
    fx3.open(0);
    uint8_t        buf[1]{0};
    const uint16_t clrChannel{0x0A};    // LED green
    fx3.vrCmd(Cmd::i2c_bridge, OpType::read, 0, clrChannel, buf, 1);
    buf[0] += buf[0] / 4;  // yes, this can totally overflow
    fx3.vrCmd(Cmd::i2c_bridge, OpType::write, buf[0], clrChannel);
}

FX3 Host Vendor Command Reference

The following tables provide information on how to access the camera's functionality for FX3 Host Vendor Command Interface. The address space is split into smaller chunks, grouped by common functionality:

0x00-0x9F

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Reserved0x00-0x9F Think of this as “system address space”

0xA0-0xA7

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Bootloader check0xA0 R/W Check if a bootloader is running, the result is in the command's status code (success/failure interpreted as true/false)
Reserved0xA1
Run DPC calibration0xA2 DPC ThresholdW/O Start the dynamic DPC calibration with the given DPC Threshold in range [0..255]
Reconfig FGPA0xA3 W/O Writing anything into this register causes the FPGA to reconfigure itself from SPI Flash
FPGA I²C Bridge0xA4FPGA register offsetFPGA data (write)W/O0 or 17:0 - FPGA dataFPGA write returns 0 byte buffer, FPGA read returns 1 byte buffer. Read/write is requested via control endpoint's direction attribute being set to DIR_FROM_DEVICE/DIR_TO_DEVICE. For more details refer to FPGA I²C bridge
RAW Mode Select0xA5 R/W 1 7:1 - Reserved
0 - RAW Mode
Select RAW Mode ('1') or Processed Video ('0')
Reserved0xA6-0xA7

0xA8-0xAF - versioning and reprogramming

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Reserved0xA8-0xA9
Erase SPI Flash0xAA W/O Any write to this location invalidates the FX3 SPI Flash and causes the FX3 to reset itself to a bootloader mode for reprogramming
FX3 version0xAB R/O431:29 Vendor ID
28:24 HW_CFG_ID
23:16 Product ID
15:11 Release type
10:0 Build number
Get detailed version information of the FX3, for more details refer to FX3 Version Info
FPGA version0xAC R/O431:29 Vendor ID
28:24 HW_CFG_ID
23:16 Product ID
15:11 Release type
10:0 Build number
Get detailed version information of the FPGA, for more details refer to FPGA Version Info
FPGA config. ctrl.0xAD W/O Any write to this location will put the FPGA into configuration mode
FPGA config. status - SPI codes0xAE R/O2 see below for details Retrieve detailed status of the FPGA configuration operation
SPI Flash write enable0xAF W/O Reconfigure the FX3 IOMatrix to disable GPIF and enable SPI

FPGA config status - SPI codes

Bit name Description
15 Program SwitchWord OK
14 Verify OK Verification succeeded
13 Program OK Programming completed successfully
12 Erase OK SPI erase was successful
11 Erase SwitchWord OK
10 Check ID OK
9 Initialize OK
8 Config started Config operation has started
7 CRC error
6 Timeout error
5 Program error Error while programming the SPI
4 Erase error Encountered an error while erasing SPI
3 IdCode error
2 Config error Configuration operation errored out
1 Config done Configuration operation is complete
0 Config not busySet to 1 while the config is not busy

0xB0-0xCF

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Reserved0xB0-0xCF

0xD0-0xD7 - Auto exposure configuration

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
AE Setpoint0xD0 AE SetpointR/W0 or 1 7:0 AE SetpointTarget Auto Exposure Luminance Setpoint [0..255]
Default: 105
This controls the “average luminance” of the whole frame that we are trying to achieve. The higher the value the brighter the result is going to be
AE Hysteresis0xD1 AE HysteresisR/W0 or 2 15:0 AE HysteresisAuto Exposure Hysteresis Value UFIX 8.8
Default 3.0
This controls how far can we diverge from the set target luminance before we begin the correction. In other words the higher this value the further we allow the luminance to drift away from the target before correcting it
AE Error Tolerance0xD2 AE Err TolR/W0 or 2 15:0 AE Err TolAuto Exposure Error Tolerance Value UFIX 8.8
Default 1.0
Specifies the “close enough” tolerance at which point the correction can be stopped. Normally this value is (at least somewhat) lower than the AE Hysteresis
AE Exposure Scaling0xD3 AE Exp ScaleR/W0 or 2 15:0 AE Exp ScaleAuto Exposure Exposure Scaling Value UFIX 8.8
Default 100.0
Controls the speed (stepping) at which the correction is happening. Higher values will result in large brightness jumps and a value too high may cause an oscillation while a value that is too low will cause the correction process to be too slow and seamingly unresponsive
AE C Gain Divisor0xD4 AE C Gain DivisorR/W0 or 2 15:0 AE C Gain DivisorAuto Exposure C Gain Divisor Value UFIX 8.8
Default 4.0
Value between 0 and 255 that is inversely proportional to the rate at which the C gain is adjusted in response to exposure errors. (i.e. the larger the value, the slower C gain will adjust)
Reserved0xD5-0xD7

0xD8-0xDE - Auto white balance configuration

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
AWB Setpoint0xD8 AWB SetpointR/W0 or 2 15:0 AWB SetpointAuto White Balance G Gain Setpoint [0..2047]
Default 1024
The pinned value for Green Gain that is used as the basis for the rest of the white balance adjustments. Only change this value if you need to make your picture brighter and you have exhausted both the Exposure and the Global Gain options
AWB Hysteresis0xD9 AWB HysteresisR/W0 or 2 15:0 AWB HysteresisAuto White Balance Hysteresis Value UFIX 8.8
Default 3.0
How far can the error drift before we start adjusting it
AWB Error Tolerance0xDA AWB Err TolR/W0 or 2 15:0 AWB Err TolAuto White Balance Error Tolerance Value UFIX 8.8
Default 1.0
A.k.a. “good enough” approximation - controls when we stop the correction process, having achieved a “close enough” result. Generally this setting is at least somewhat lower than the AWB Hysteresis value
AWB Adjustment Scaling0xDB AWB Adj ScaleR/W0 or 2 15:0 AWB Adj ScaleAuto White Balance Adjustment Scaling Value UFIX 8.8
Default 4.0
Value between 0 and 255 that is inversely proportional to the rate at which the R and B gains are adjusted in response to white balance errors. (i.e. the larger the value, the slower R and B gains will adjust)
Reserved0xDC-0xDE

0xDF - Auto-functions' timing

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
Auto Update Period0xDF Auto Update PeriodR/W0 or 2 15:0 Auto Update PeriodAuto Update Period [0..65535])
Default 3000
Determines how long we wait before trying to apply a new update for both exposure and white balance (when auto functions are enabled). This is an asynchronous update rate (i.e. not an absolute time, but larger values should mean slower updates)

0xE0-0xFF

Name Offset wIndex wValue Access type Byte length Return buffer bits Notes
FX3 reset0xE0 R/W Cypress vendor command to soft reset FX3
Reserved0xE1-0xFF

FPGA I²C bridge

The following tables provide information on how to access the camera's functionality for an FPGA I²C bridge.

Here's a sample code (skipping all error checking) that sets the LED to bright-yellow color:

S2R::FX3 dev; // auto-open device #0
using S2R::FX3;
dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 255, 0x08); // red
dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 255, 0x0A); // green
dev.vrCmd(FX3Cmd::i2c_bridge, VrCmdOpType::write, 0, 0x0C);   // blue

The address space is broken down into smaller chunks, grouped by common functionality:

0x00-0x07 - FPGA general access

Name Offset Access Bit mapping Notes
FPGA Version #00x00R/O7:5 Vendor ID
4:0 HW_CFG_ID
FPGA Version #10x01R/O7:0 Product ID
FPGA Version #20x02R/O7:3 Release type
2:0 Build number MSB
Build number is split into 2 MSB and 8 LSB for a combined total width of 10 bits
FPGA Version #30x03R/O7:0 Build number LSB
FPGA config status #00x04R/Osee SPI codes for detailsLSB (bits 7-0) of the FPGA config status
FPGA config status #10x05R/Osee SPI codes for detailsMSB (bits 15-8) of the FPGA config status
FPGA control0x06R/W Global control of the FPGA's functionality
7 FPGA config enableIf bit 7 is set, the GPIF becomes read only and waits for an update bitstream
6 Reserved
5 RAW ModeSetting bit 5 and clearing bit 0x06::2 will enable RAW mode output (4K Only)
4 Video FormatBit 4 selects between NV12 ('1') and YUY2 ('0') output formats
3 DPC enableSetting bit 3 along with bit 0x06::0 will perform a DPC correction
2 HSUB enableBit 2 is to enable/disable Horizontal Subsampling
1 Audio enableBit 1 is to enable/disable on-board microphones
0 Video enableBit 0 enables/disables video streaming
Reserved0x07

0x08-0x0D - LED

Name Offset Access Bit mapping Notes
LED_RED_L0x08R/W7:0 Red LEDLSB of LED's red intensity in range [0..255]
LED_RED_H0x09R/WReserved
LED_GREEN_L0x0AR/W7:0 Green LEDLSB of LED's green intensity in range [0..255]
LED_GREEN_H0x0BR/WReserved
LED_BLUE_L0x0CR/W7:0 Blue LEDLSB of LED's blue intensity in range [0..255]
LED_BLUE_H0x0DR/WReserved

0x0E-0x0F - Noise Reduction

Name Offset Access Bit mapping Notes
NR Control0x0ER/W7:1 Reserved
0 NR Enable '1' ⇒ NR enabled, '0' ⇒ NR disabled
NR Threshold0x0FR/W7:0 NR ThresholdNoise level threshold in range [0..255]

0x10-0x1F - Basic UVC controls

Name Offset Access Bit mapping Notes
Brightness_L0x10R/W7:0 LSB16 bits of brightness are split into 8 bits of LSB and MSB
Brightness_H0x11R/W7:0 MSB
Contrast_L0x12R/W7:0 LSB16 bits of contrast are split into 8 bits of LSB and MSB
Contrast_H0x13R/W7:0 MSB
Saturation_L0x14R/W7:0 LSB16 bits of saturation are split into 8 bits of LSB and MSB
Saturation_H0x15R/W7:0 MSB
Sharpness_L0x16R/W7:0 LSB16 bits of sharpness are split into 8 bits of LSB and MSB
Sharpness_H0x17R/W7:0 MSB
Gamma_L0x18R/W7:0 LSB16 bits of gamma are split into 8 bits of LSB and MSB
Gamma_H0x19R/W7:0 MSB
Hue_L0x1AR/W7:0 LSB16 bits of hue are split into 8 bits of LSB and MSB
Hue_H0x1BR/W7:0 MSB
Reserved0x1C-0x1F

0x20-0x27 - Defective pixel cancellation

Name Offset Access Bit mapping Notes
DPC Threshold LSB0x20R/W7:0 LSB 16 bit of DPC (defective pixel cancellation) Threshold are split into 8 bits of LSB and MSB
DPC Threshold MSB0x21R/W7:0 MSB
DPC count LSB0x22R/O7:0 LSBOnce the DPC calibration is done the 16-bit value is stored in these 2 registers
DPC count MSB0x23R/O7:0 MSB
Reserved0x24-0x27

0x28-0x2F - General image statistics

Name Offset Access Bit mapping Notes
Y average0x28R/O7:0 value
U average0x29R/O
V average0x2AR/O
R average0x29R/O7:0 valuean average RGB value
G average0x2AR/O7:0 value
B average0x2BR/O7:0 value
Reserved0x2C-0x2F

0x30-0x3F - GPIO

Name Offset Access Bit mapping Notes
CAM_GPIO_L0x30R/Wreserved
CAM_GPIO_H0x31R/Wreserved
CAM_GPIO_DIR_L0x32R/Wreserved
CAM_GPIO_DIR_H0x33R/Wreserved
CAM_GPIO_OE_L0x34R/Wreserved
CAM_GPIO_OE_H0x35R/Wreserved
Reserved0x36-0x3F

0x40-0x7F - On-board compression

Name Offset Access Bit mapping Notes
H.264 QP0x40R/W7:6 reserved
5:0 value
Valid range for the H.264 QP value is [0..51]
Reserved0x41-0x7F

0x80-0xBF - Green Screen enhancer

“Green screen”, a.k.a. “Chroma Key” on-board optimization is designed to replace a range of colors with a single solid one

0x80-0x8F - band #0

If enabled these setting take precedence over other 3 bands

Name Offset Access Bit mapping Notes
CK control0x80R/W7:1 reserved
0 enable
enable/disable Chroma Key control
CK status0x81 reserved
CK saturation min0x82R/W7:0 sat. min[0..255] to specify the minimum saturation threshold
CK saturation max0x83R/W7:0 sat. max[0..255] to specify the maximum saturation threshold
CK luma min0x84R/W7:0 luma min[0..255] to specify the minimum brightness threshold
CK luma max0x85R/W7:0 luma max[0..255] to specify the maximum brightness threshold
CK hue LSB0x86R/W7:0 hue LSB14 bits of a signed hue value are split into 8 LSB and 6 MSB, its [-8K..+8K] range is mapped into [-180°..+180°]
CK hue MSB0x87R/W7:6 reserved
5:0 hue MSB
CK tolerance LSB0x88R/W7:0 tolerance LSB13 bits of an unsigned hue tolerance value are split into 8 LSB and 5 MSB, valid range is [0..8K], which is mapped into [0°..180°].
That value specifies how far to stretch the CK hue value both ways (symmetrically). If the CK tolerance is above 90° the covered color space is over 50% of values
CK tolerance MSB0x89R/W7:5 reserved
4:0 tolerance MSB
CK red LSB0x8AR/W7:0 red LSB
CK red MSB0x8BR/Wreserved
CK green LSB0x8CR/W7:0 green LSB
CK green MSB0x8DR/Wreserved
CK blue LSB0x8ER/W7:0 blue LSB
CK blue MSB0x8FR/Wreserved

0x90-0x9F - band #1

Color substitution (if enabled) takes place after the first band had a chance to process the pixels

The layout of the settings is identical to that of band #0 just shifted down by a paragraph and occupying address block 0x90-0x9F

0xA0-0xAF - band #2

Color substitution (if enabled) takes place after the first and second bands had a chance to process the pixels

The layout of the settings is identical to that of band #0 just shifted down by 2 paragraphs and occupying address block 0xA0-0xAF

0xB0-0xBF - band #3

Color substitution (if enabled) takes place after other bands had a chance to process the pixels

The layout of the settings is identical to that of band #0 just shifted down by 3 paragraphs and occupying address block 0xB0-0xBF

0xC0-0xFF - Reserved

This is where future API will land. Stay tuned ;-)

FX3 Version Info

Vendor ID

Code Value
1Cypress

Hardware ID

Code Value
1FX3

Product ID

Code Value
1reserved for Gen 1 camera, a.k.a. “Moon landing”
2reserved for Gen 2 camera, a.k.a. “Piggy”
3Gen 3 camera (Alpha), a.k.a. “Frankie” (from Frankenstein)
4Gen 3 camera, RC1
5Gen 3 camera, RC2
6Gen 3 camera, Production (reserved)

Release type

Code Name Meaning
1Alpha feature-incomplete early development cycle “somewhat stable” build
2Beta feature-complete, but not very stable build (lots of bugs)
3Evaluation Tech preview
4Release candidate feature complete and stable
5Release general availability
6Backport backport of a feature from next gen camera
7Emergency bug fix a critical post-release bugfix

Build number

Code Value
#Increments on each build

FPGA Version Info

Vendor ID

Code Value
1Xilinx

Hardware ID

Code Value
1Artix 100T
2Artix 200T

Product ID

Code Value
1reserved
2reserved
3Gen 3 camera (Alpha), a.k.a. “Frankie”
4Gen 3 camera, RC1
5Gen 3 camera, Production (reserved)

Release type

Code Value
1Alpha
2Beta
3Eval/Tech preview
4Release candidate
5Release
6Backport
7Emergency bug fix

Build number

Code Value
#Increments on each build
/home/adminsub2r/public_html/dokuwiki/data/pages/code/fx3_hvci_and_fpga_i_c_commands.txt · Last modified: 2018/09/30 20:21 by Igor Yefmov