To control FPGA's functionality a whole lot of registers are defined which are accessible via I2C bus but the method differs drastically in address/data width. Both Xilinx-based Gen 3 and Gen 4 FPGAs are using 8-bit address and data whereas Gen 5 is using Intel's Avalon bus which is based on 32 bit address and data. The FPGA register maps are defined in these specs:
   - [[fpga_map_gen3_and_4|Gen 3 and 4]]
   - [[fpga_map_gen5|Gen 5]]

The registers' maps between different version of cameras should be treated as incompatible.